GlobalFoundries has plans to deploy Everspin's perpendicular (pMTJ) STT-MRAM as an embedded 22nm memory - as part of GF's 22FDX platform. GlobalFoundries has released a technical paper that details the eMRAM ability to retain data at high temperatures.

The eMRAM can retain data through solder reflow at 260 degrees Celsius, and for more than 10 years at 125 degrees Celsius, plus read/write with outstanding endurance at 125 degrees Celsius. GlobalFoundries says that this will enable eMRAM to be used for general purpose MCUs and automotive SOCs.

During Samsung Electronic's Foundry Forum, the Korean chip maker reaffirmed its goal to start producing STT-MRAM chips in 2018. In fact Samsung now says that it will mass produce these chips next year, while last year it said that 2018 will only see limited production while real mass production will only begin in 2019.

Samsung announced it will produce the 2018 MRAM chips will be produced using 8-nano low power plus (8LMPP) semiconductor foundry process. Samsung sees MRAM produced by 4LPP by 2020.

Luc Thomas from Headway, a TDK-owned recording head designer and producer, explains the basic principles and challenges of STT-MRAM for embedded memory applications:

This lecture was given at the MSST 2017 Mass Storage Conference (May 15 — 19, 2017).

Everspin announced several new applications and customers for its MRAM solutions. First up is the new nvNITRO storage accelerator product family. These new cards (aimed for demanding applications such as financial transactions) are available in either 1Gb or 2Gb, and are based on Everspin's 256Mb DDR STT-MRAM chips. Later this year Everspin will release new models based on its 1Gb DDR4 chips which will enable capacities up to 16Gb.

Everspin says that the nvNITRO operate at a very fast 1,500,000 IOPS with 6-ms end-to-end latency. Everspin is testing the first cards at customers now, and initial production will begin in Q2 2017.

Spin Transfer Technologies announced that it started to deliver fully functional ST-MRAM samples to customers in North America and Asia.

The sample devices are based on the company's Orthogonal Spin Transfer Magneto-Resistive Random Access Memory technology (OST-MRAM), and use 80nm perpendicular magnetic tunnel junctions (MTJs)., the latest generation of MRAM technology.

Toshiba and SK Hynix co-developed a 4-Gbit STT-MRAM chip, and presented a prototype at IEDM 2016.

The prototype chip is made from eight 512-Mbit banks, and the cell area is equivalent to that of DRAM - at 9F2, which Hynix says is much smaller than conventional STT-MRAMs (50F2).

Samsung demonstrated an LCD display that uses a tCON chip that uses embedded 28nm pMTJ STT-MRAM memory, instead of the normally used SRAM. The MRAM device had a density of 8Mb and a 1T-1MTJ cell architecture. The cell size is 0.0364 um².

A tCON chip is a timing controller chip that processes the video signal input and processes it to generate control signal to the source & gate driver of the LCD display. The memory is used a a frame memory which stores previous frame data. Samsung prepared a test chip that contains both SRAM and MRAM memory devices to show that there is no difference between the two. SRAM replacement is a popular MRAM application.

Researchers at IMEC developed a 8nm perpendicular magnetic tunnel junction (pMTJ) with 100% tunnel magnetoresistance (TMR) and a magnetic coercive field up to 1,500 Oe in strength. The researchers also demonstrated integrated 1Mbit STT-MRAM 1T1MTJ arrays with pitches down to 100 nm.

IMEC says that this is the world's smallest pMTJ - which paves the way for high density stand-alone MRAM applications. The pMTJ was developed on 300mm silicon wafers in a production process that is compatible with the thermal budget of standard CMOS back-end-of-line technology.

In 2015, the EU launched the GREAT project, with an aim to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting STT-MTJs to a single baseline technology in the same system on chip. GREAT stands for heteroGeneous integRated magnetic tEchnology using multifonctionnal stAndardized sTack.

The project partners now announced the first hybrid CMOS/MSS-MRAM Tape Out with Israel-based Tower Jazz. This hybrid integrated circuit uses the 180nm CMOS process from Tower and an academic MRAM post-process that will be done by CEA Spintec within their facilities.

Capres A/S was established in 1999 in Denmark to develop a unique probe technology designed for in-line production monitoring in the semiconductor industry. The company, in collaboration with IBM, developed a resistivity measurement technique to characterize MTJ stacks.

Bo Svarrer Hansen, the company's CEO since 2002, was kind enough to answers a few questions we had, and share with us his views on the MRAM market and the company's measurement systems for MRAM and STT-MRAM device developers.

Q: Can you update us on Capres' current offers to the MRAM industry?

Capres customers are using our CIPTech® tools for R&D on small samples as well as volume production on 300 mm wafers. Depending on the configuration the tools measure with an in- plane or an out- of- plane magnetic field on blanket as well as patterned wafers.