Article last updated on: Feb 19, 2019

STT-MRAM (also called STT-RAM or sometimes ST-MRAM and ST-RAM) is an advanced type of MRAM devices. STT-MRAM enables higher densities, low power consumption and reduced cost compared to regular (so-called Toggle MRAM) devices. The main advantage of STT-MRAM over Toggle MRAM is the ability to scale the STT-MRAM chips to achieve higher densities at a lower cost.

STT-MRAM has the potential to become a leading storage technology as it is a high-performance memory (can challenge DRAM and SRAM) that can scale well below 10nm and challenge the low cost of flash memory.

What is STT-MRAM?

STT stands for Spin-Transfer Torque. In an STT-MRAM device, the spin of the electrons is flipped using a spin-polarized current. This effect is achieved in a magnetic tunnel junction (MTJ) or a spin-valve, and STT-MRAM devices use STT tunnel junctions (STT-MTJ). A spin-polarized current is created by passing a current though a thin magnetic layer. This current is then directed into a thinner magnetic layer which transfers the angular momentum to the thin layer which changes its spin.

STT-MRAM structure diagram

What is perpendicular STT-MRAM?

A "regular" STT-MRAM structure (similar to the one you see above) uses an in-plane MTJ (iMTJ). Some STT-MRAM devices use a more optimized structure called perpendicular MTJ (pMTJ) in which the magnetic moments are perpendicular to the silicon substrate surface.

Perpendicular STT-MRAM is more scalable compared to iMTJ STT-MRAM and is also more cost competitive. Perpendicular STT-MRAM is thus a more promising technology to replace DRAM and other memory technologies



STT-MRAM chips

Several companies, including IBM and Samsung, Everspin, Avalanche Technologies, Spin Transfer Technologies and Crocus are developing STT-MRAM chips. In April 2016 Everspin announced that it started shipping 256Mb ST-MRAM samples to customers. The new chips demonstrate interface speeds comparable to DRAM, with DDR3 and DDR4 interfaces. Volume production is expected "soon".

Everspin EMD3D256 256Mb ST-MRAM photo

In August 2016 Everspin started sampling pMTJ-based ST-MRAM chips. The first chips are also 256Mb in size, but the pMTJ versions offer improved performance, higher endurance, lower power, and better scalability compared to previous iMTJ ST-MRAM products. Everspin is now ramping out 256Mb pMTJ ST-MRAM production and is developing a scaled-down 1Gb version.

The latest STT-MRAM news:

Avalanache Technology's Serial P-SRAM STT-MRAM memory devices are now shipping

pMTJ STT-MRAM developer Avalanche Technology announced that its new industrial-grade Serial (SPI) P-SRAM (Persistent SRAM) memory devices are now available. The Serial (SPI) memory devices are designed to be drop-in replacements to Cypress F-RAM and Everspin Toggle MRAM memory products.

Avalanche pMTJ STT-MRAM P-SRAM Serial QSPI Evaluation Kit photo

The Series (SPI) series supports up to 50MHz clock rate in 1Mb and 4Mb density options, in two packages - 8-pin SOIC and 8-pin WSON. These use Avalanche's 40nm pMTJ STT-MRAM chips.

Successful MRAM Production Requires Good Magnetic Test Equipment

This is a sponsored post by Integral Solutions Int'l

MRAM is likely to be the most promising next-generation non-volatile memory technology today. Toggle MRAM and STT-MRAM are already entering the market, gaining market share in many applications. Next-generation MRAM technologies, such as SOT-MRAM could enable the replacement of even the fastest SRAM applications, with higher densities.

MRAM Manufacturing Process Flow (Coughlin)Source: Coughlin Associates, 2019

The MRAM production process has many stages, as device architecture is relatively complex, with a magnetic cell (frontplane) fabricated on top of a CMOS backplane. (use Figure 2 or Figure 3 from Coughlin). Measurement and characterization of devices are highly important, and the production of MRAM memories depend on measurement tools are are specialized for MRAM and STT-MRAM measurements.

Everspin and Globalfoundries extend their MRAM agreement to 12 nm processes

Everspin Technologies announced that it has amended its STT-MRAM joint development agreement (JDA) with GLOBALFOUNDRIES to set the terms for a future project on an advanced 12 nm FinFET MRAM solution. Everspin agreement included 40 nm, 28 nm and 22 nm processes, and now also include 12 nm.

Everspin 1Gb STT-MRAM chip photo

GF recently announced it has achieved initial production of embedded MRAM (eMRAM) on its 22FDX platform.

Researchers show how antiferromagnetic STT-MRAM technology can enable higher-density and lower energy memory

Researchers from Northwestern University suggest building STT-MRAM devices from antiferromagnetic materials - as opposed to the currently-used ferromagnetic ones. The researchers say that these materials will enable higher-density devices that feature high speed writing with low currents.

Antiferromagnetic materials are magnetically ordered at the microscopic scale, but not at the macroscopic scale. This means that there is no magnetic force between adjacent bits in MRAM cells built from these materials - which means you can pack them very close together.

New super-lattice SL-STT-MRAM enable faster and more efficient memory architecture

Researchers from the National Taiwan University developed a new ultra low power STT-MRAM architecture, called Super Lattice STT-MRAM, or SL-STT-MRAM. The researchers say that SL-STT-MARM simultaneously achieves ultra-high MR ratio, high-speed switching, and low RA.

SL STT MRAM structure

An SL-STT-MRAM is based on an SL-STT-MTJ, which uses a superlattice barrier to replace the single crystalline (MgO) barrier in traditional STT-MTJ. The superlattice barrier is made of alternating metal and insulator layers, in which only amorphous rather than single crystalline is used in the insulator. The SL-STT-MRAM features higher reliability for repeated writing than compared to traditional MgO based STT-MRAM.

Intel researchers demonstrate 2MB STT-MRAM arrays suitable for on-chip L4 cache applications

Intel researchers have demonstrated 2MB STT-MRAM devices that are suitable for on-chip L4 cache applications. Intel says these devices feature data retention, endurance and bit error rates good enough for L4 cache.

Intel slide - STT MRAM L4 Cache

Intel's new STT-MRAM features 20 nm write times, 4 ns read times, an endurance of 1012 cycles and memory retention of one second at 110 degrees. The bit rates are good enough to be handled with error-correcting code (ECC) techniques. To achieve these features, Intel reduced the magnetic junction size to 55 nm (from 70-80 nm it had achieved before).

Everspin announces its Q3 2019 financial results

Everspin Technologies announced its financial results for Q3 2019 - with revenues of $9.2 million (down from $11.5 million in Q3 2018) and a net loss of $3.7 million (down from $5.6 million in Q3 2018). Everspin says that it achieved record STT-MRAM revenues.

At the end of the quarter, Everspin had $14.8 million in cash and equivalents. For the next quarter, it expects revenues to be between $9.3 million and $9.7 million.

IBM to use Everspin's 1Gb STT-MRAM in its next-gen FlashCore modules

In August 2018 IBM announced that it adopted Everspin's 256Mb STT-MRAM chips in its enterprise SSD FlashSystem. Now IBM announced that it's latest FlashCore modules will use Everspins 1Gb STT-MRAM chips.

Everspin 1Gb STT-MRAM chip photo
Using MRAM instead of DRAM memory enabled IBM to remove the relatively large supercapacitors (used to make the DRAM non-volatile) and so the company was able to reduced the size of its drives and switch to a standard 2.5-inch U.2 drive form factor.