Article last updated on: Feb 19, 2019

STT-MRAM (also called STT-RAM or sometimes ST-MRAM and ST-RAM) is an advanced type of MRAM devices. STT-MRAM enables higher densities, low power consumption and reduced cost compared to regular (so-called Toggle MRAM) devices. The main advantage of STT-MRAM over Toggle MRAM is the ability to scale the STT-MRAM chips to achieve higher densities at a lower cost.

STT-MRAM has the potential to become a leading storage technology as it is a high-performance memory (can challenge DRAM and SRAM) that can scale well below 10nm and challenge the low cost of flash memory.

What is STT-MRAM?

STT stands for Spin-Transfer Torque. In an STT-MRAM device, the spin of the electrons is flipped using a spin-polarized current. This effect is achieved in a magnetic tunnel junction (MTJ) or a spin-valve, and STT-MRAM devices use STT tunnel junctions (STT-MTJ). A spin-polarized current is created by passing a current though a thin magnetic layer. This current is then directed into a thinner magnetic layer which transfers the angular momentum to the thin layer which changes its spin.

STT-MRAM structure diagram

What is perpendicular STT-MRAM?

A "regular" STT-MRAM structure (similar to the one you see above) uses an in-plane MTJ (iMTJ). Some STT-MRAM devices use a more optimized structure called perpendicular MTJ (pMTJ) in which the magnetic moments are perpendicular to the silicon substrate surface.

Perpendicular STT-MRAM is more scalable compared to iMTJ STT-MRAM and is also more cost competitive. Perpendicular STT-MRAM is thus a more promising technology to replace DRAM and other memory technologies



STT-MRAM chips

Several companies, including IBM and Samsung, Everspin, Avalanche Technologies, Spin Transfer Technologies and Crocus are developing STT-MRAM chips. In April 2016 Everspin announced that it started shipping 256Mb ST-MRAM samples to customers. The new chips demonstrate interface speeds comparable to DRAM, with DDR3 and DDR4 interfaces. Volume production is expected "soon".

In August 2016 Everspin started sampling pMTJ-based ST-MRAM chips. The first chips are also 256Mb in size, but the pMTJ versions offer improved performance, higher endurance, lower power, and better scalability compared to previous iMTJ ST-MRAM products. Everspin is now ramping out 256Mb pMTJ ST-MRAM production and is developing a scaled-down 1Gb version.

The latest STT-MRAM news:

Orthogonal Spin Transfer MRAM developer Spin Memory liquidates

Orthogonal Spin Transfer MRAM (OST-MRAM) technology developer Spin Memory is shutting down. The company's main investor and founding company, Allied Minds, said in a statement that the main reasons challenges in securing new customers and COVID-19 which "significantly delayed the required testing of its development chip with ARM".

MRAM by Spin Memory photo

This is a sad ending to Spin Memory, which began its way as Spin Transfer Technologies - a spin-off from NYU that was established together with Allied Minds.

Avalanche announces space-grade Gigabit-density STT-MRAM

pMTJ STT-MRAM developer Avalanche Technology announced its third-generation 1Gb space-grade parallel asynchronous x32-interface high-reliability P-SRAM (Persistent SRAM) memory devices. The company says that these new devices enable customers to design unified memory architecture systems for high reliability aerospace applications, in extremely small form factors.

Avalanche pMTJ STT-MRAM P-SRAM Serial QSPI Evaluation Kit photo

Avalanche's 2nd-Gen P-SRAM evaluation kit

The new Parallel x32 Space Grade series is offered in 512Mb, 1Gb, 2Gb and 4Gb density options and has asynchronous SRAM compatible 45ns/45ns read/write timings. Data is always non-volatile with >10^14 write cycles endurance and 10-year retention at 125°C. All four density options are available in a small footprint 142-Ball FBGA (17mm x 11mm) package.

Avalanche starts production of space-grade 16-64Mb STT-MRAM devices

pMTJ STT-MRAM developer Avalanche Technology announced that it is now shipping new space-grade parallel asynchronous x16-interface high-reliability P-SRAM (Persistent SRAM) memory devices, based on its latest STT-MRAM technology.

Avalanche pMTJ STT-MRAM P-SRAM Serial QSPI Evaluation Kit photo

Avalanche says that its STT-MRAM devices are smaller and more efficienct compared to Toggle MRAM based products, currently adopted in aerospace applications. The Parallel x16 Space Grade series is offered in 16Mb, 32Mb and 64Mb density options and has asynchronous SRAM compatible 45ns/45ns read/write timings. All three density options currently in production and available within industry standard lead times.

ISI ships its first SOT-MRAM tester system

Integral Solutions International (ISI) announced its first shipment of a commercial SOT-MRAM tester system. This new equipment was developed by integrating a commercial pulser with ISI’s proprietary bias-tee and measurement electronics.

ISI says that the new tester system generates pulses as narrow as 300pS, suitable for R&D applications which require extremely narrow pulse widths. In parallel, ISI is also developing its proprietary Gen-4 Pulser System, which will provide high-throughput and cost-effective measurement solutions with the flexibility of testing either STT-MRAM or SOT-MRAM devices. The Gen-4 system is expected to be released in the fall of 2021.

Everspin reported its preliminary Q4 2020 and full-year 2020 financial results

Everspin Technologies announced its preliminary Q4 2020 financial results. Total revenues were $10 million, down from $10.1 million in Q3 and up from $9.7 million in Q4 2019. Net loss int he quarter was $1.6 million, but the company generated $0.6 million in cash flow - Everspin's second consecutive positive cash flow from operations quarter.

Everspin Technologies chip photo

Looking at FY2020, Everspin's revenues increased 12.1% to $42 million. At the end of the year, Everspin had $14.6 million in cash and equivalents. In Q4 2020, the company also received its first royalty revenue from GF for embedded 22FDX process MRAM.

IBM to reveal the world's first 14nm STT-MRAM node

IBM announced that during the 2020 IEEE International Electron Devices Meeting (IEDM 2020), that is now being held virtually, its researchers will reveal the first 14 nm node STT-MRAM. IBM says that efficient and high-performance STT-MRAM systems will help to address memory-compute bottlenecks in hybrid cloud systems.

IBM says that the 14 nm node embedded MRAM which will be revealed is the most advanced MRAM demonstrated to date. It features circuit design and process technology that could soon enable system designers to replace SRAM with twice the amount of MRAM in last-level CPU cache.

Everspin reports its financial results for Q3 2020, is cash flow positive for the first time ever

Everspin Technologies announced its Q3 2020 financial results, with revenues of $10.1 million, up 10% from Q3 2019 ($9.2 million) but down $14% from Q2 2020 ($11.8 million). The company's net less was $3.9 million.
Everspin Technologies chip photo

Looking at the balance sheet, Everspin reports a cash flow of $1 million in the quarter - this was the first quarter ever for Everspin to have a positive cash flow.

Numem to supply its STT-MRAM to a NASA AI core project

High-performance STT-MRAM developer Numem announced that it has been selected for a NASA AI project, for which the company will supply its Numem NuRAM MRAM-based Memory. Numem says its memory enables a 2-3x smaller memory area and 20x to 50x lower standby power compared to SRAM.

The project, titled “DNN Radiation Hardened Co-processor as companion chip to NASA’s upcoming High-Performance Spaceflight Computing Processor” will develop a reconfigurable DNN Engine with multiple compute units which can support a wide range of DNN models and frame rates.

Superlattice and half-metallic magnets used to developed SS-MRAM, an ultra-high performance MRAM device

Researchers from the National Taiwan University developed an ultra-high performance MTJ, using a superlattice barrier and half-metallic magnets. The so-called superlattice-MTJ can be the basis of a new class of STT-MRAM (which the researcher call SS-MRAM) that achieves ultra-low power RA and write operations, high writing speed and unlimited endurance.

Geometric structure of a three-cell superlattice MTJ (National Taiwan University)

SS-MRAM adopts a superlattice barrier that replaces the MgO layer used in common STT-MRAM. The MgO layer is unstable and also suffers from a very large RA which results in high power consumption for writing operations. The superlattice has higher spin polarization than MgO and so the SS-MARM can provides not only ultra-high MR ratio but also ultra-low RA for high-speed and low power writing.