Spingate is a US-based company focusing on perpendicular MRAM technologies. In November 2009 we have talked to Dr. Alex Shukh, Spingate's co-founder, CTO and CEO, and he explains Spingate's technology . Today Spingate sent us another update.

Spingate says that since 2009 they continued to build their IP portfolio. The company invented and has been developing a new class of nonvolatile spin logic that combines advantages of conventional CMOS logic and MRAM technologies. Spingate's spin logic represents an elegant synthesis of the conventional logic with embedded MRAM cells residing above the silicon. The memory cells have a marginal impact on layout of the logic but provides it with a non-volatility. The spin logic may offer significant performance enhancements of conventional logic devices by eliminating numerous off-chip data flows resulting in speeding up the entire system. The embedded MRAM cells employ spin induced switching mechanism and magnetic materials with either in-plane or perpendicular anisotropy. The spin logic employing perpendicular magnetic materials has better scalability and lower switching current than that based on in-plane materials. The company's logic is especially attractive for application in field programmable gate arrays (FPGAs) due to its non-volatility, simplicity, high speed and reduced chip size. Moreover it can be used for creation of nonvolatile micro-controllers and microprocessors.

Spingate has been also developing a proprietary 3rd generation of MRAM technology that is based on the spin induced switching and perpendicular magnetic materials (pS-MRAM). The company invented a MRAM cell with a new writing mechanism that provides high switching speed along with a reduced spin polarized current; and an elegant design and manufacturing process for perpendicular magnetic tunnel junctions with tunneling magnetoresistance exceeding 100%.

The most recent Spingate's accomplishment is an invention of pS-MRAM with a cell size of 4F2 in 2D configuration. That is the smallest memory cell size in the industry. This design can be transformed easily into 3D architecture. As a result of this transformation, the effective cell size would be reduced up to 1F2 or up to 0.5F2 with four or eight layers of magnetic tunnel junctions, respectively. The company is working now on a design of 4Gbit chip built with 65nm technology node. The chip size is around 113 mm2 with a spin polarized write current of 35 µA and write time less than 10 ns. Parameters of the chip are comparable to those of the most advanced DRAM chips currently available on the market that are built with more expensive 45nm node. The company's technology is scalable up to 32nm and beyond. It's competitive in performance and price/bit with all existing memory technologies including DRAM and NAND flash.