MRAM (Magnetoresistive Random Access Memory) is a next-generation spintronics memory technology, based on electron spin rather then its charge. The adoption of MRAM is on the rise, with an expanding industry and market, driven by . This growth is driven by MRAM's high-speed, energy efficiency, and non-volatile data retention. MRAM-Info, established in 2004, is the world's leading MRAM industry portal.
Avalanche Technology is introducing its next-generation VNX+ storage module, that is designed specifically for military and Low Earth Orbit (LEO) environments.
Avalanche says that its new solution delivers unparalleled radiation immunity, survivability in congested electromagnetic environments, and highest-reliability performance, based on the company's Space Grade MRAM.
On January 28, Avalanche Technology filed a lawsuit in the United States District Court for the District of Delaware, against Everspin Technologies saying that Everspin's STT-MRAM technology infringes upon Avalanche's patents.
Avalanche says that there are 4 patents that Everspin infringes upon : U.S. Patents 9,318,179, 9,419,210, 11,678,586, and 10,490,737. The Lawsuit requests customary remedies for patent infringement and the ITC Complaint requests that the U.S. ITC Investigation commence an investigation.
China-based MRAM developer Truth Memory Corporation announced that it has successfully demonstrated the world's first 8 Mb SOT-MRAM chip, using a 110 nm technology node.
TMC developed a fully-integrated wafer-level SOT-MRAM manufacturing flow based on an autonomous 8-inch platform compatible with mainstream CMOS back-end processes. TMC says that through optimized magnetic stack engineering and low-damage etching with precise sidewall passivation, it has developed high-performance SOT-MTJ arrays with 150 nm.
pMTJ STT-MRAM developer Avalanche Technology announced that it has joined forces with NHanced Semiconductors to build a new rad-hard system-in-package FPGA integration designed to enable satellite and defense missions with dependable standby capability and high-confidence operational performance.
US-based NHanced Semiconductor, an advanced packaging foundry specializing in leading-edge BEoL semiconductor technologies, selected Avalanche MRAM as its partner, saying that Avalanche's memory architecture is radiation-immune, with error detection and correction built directly into the memory die. This allows radiation-induced errors to be handled seamlessly without system resets or data loss, reducing the complexity of integration and ensuring the boot memory operates reliably in harsh space environments.
Back in 2011, Russia's state-owned VC RusNano invested $125 million into MRAM developer Crocus, aiming to bring MRAM manufacturing into Russia. The project did not succeed, and the proposed fab never saw the light of day and Crocus did not stay in business.
According to a report in Russia, RusNano is now suing its former chief Anatoly Chubais, and other ex-managers, seeking $150 million in damages. It claims these losses were caused by "unreasonable and irresponsible decisions" made by the fund's managers.
Researchers from the Institute of Science Tokyo (formerly Tokyo Tech), in collaboration with Western Digital, developed a new MRAM free layer with a giant perpendicular magnetic anisotropy, with the potential scaling to CMOS 5 nm process. This is said to be the most advanced MRAM free layer to date.
The researchers explain that by using the Boron-rich Co19Fe56B25 layer in combination with the Boron-blocking Mo underlayer and the spinel MgAl2O4 oxide layer, they have realized giant perpendicular magnetic anisotropy in CoFeB with Hk as high as 17.5–19.5 kOe (x 3 improvement) and Keff as high as 6.9 -9.4 × Merg cm−3 (x 2 improvement).
Everspin Technologies announced its newest high-reliability additions to the PERSYST MRAM product line: the EM064LX HR and EM128LX HR devices. These two new xSPI MRAM products are designed for extreme operating environments, with high endurance, temperature performance and data retention. Everspin is targeting aerospace, defense, automotive and high-end industrial applications for these new chips.
Everspin's new MRAM chips have received an AEC-Q100 Grade 1 qualification for operation from -40°C to +125°C. Each device undergoes a 48-hour burn-in process and provides 10-year data retention at 125°C, ensuring predictable performance even under the most demanding conditions. With 64- and 128-megabit densities achieving 90 Mbytes/sec read and write bandwidth, sustained for over a decade, the EM064LX HR and EM128LX HR are built for systems that cannot risk data loss or degradation.
Everspin Technologies announced its financial results for Q3 2025, with revenues of $14.1 million (up 16% from $12.1 million in Q3 2024), non-GAAP net income of $1.5 million, and a net income of $54,000 (down from $2.3 million last year). At the end of the quarter, Everspin had $45.3 million in cash and equivalents - up $0.3 million in the quarter.
Everspin says that the strong sales were driven by high demand from its Low Earth Orbital Satellite, Casino Gaming and Energy Management segments. Its data center business remains strong with continued demand for toggle MRAM products for redundant array of independent disks or RAID from a broad selection of data center customers, including Dell, Supermicro, and others.
Frontgrade Technologies announced that it has expanded its MRAM product line, adding two new series, the Dual Quad Serial Peripheral Interface (Dual QSPI) series and the Parallel series. With these new MRAM chips, Frontgrade is targeting aerospace, defense, and industrial applications.
The Dual QSPI series, powered by STT-MRAM, offers a wide range of densities, 128Mb and 1/2/4/8Gb. These new devices bring flash-like non-volatility with SRAM-level speed and endurance. The Dual QSPI interface enables high-speed, synchronous communication and seamless integration into new or existing architectures. These memory chips are designed for boot, configuration, code execution, and data logging.
Researchers from Intel, in collaboration with researchers at Georgia Institute of Technology designed a new SOT-MRAM device at 7 nm. This work spans the entire project range, from device-level characteristics to system-level power performance area.
Based on ASAP7 PDK design rules, the researchers created the bit-cell and peripheral layouts for SOT-MRAM and designed the entire array. Based on place and route, the system-level PPA was calculated for various memory capacities, demonstrating bit-densities up to 14.8 Mb/mm2 and read bandwidths up to 2.98 GB/s.
