Researchers from the Institute of Science Tokyo (formerly Tokyo Tech), in collaboration with Western Digital, developed a new MRAM free layer with a giant perpendicular magnetic anisotropy, with the potential scaling to CMOS 5 nm process. This is said to be the most advanced MRAM free layer to date.

The researchers explain that by using the Boron-rich Co₁₉Fe₅₆B₂₅ layer in combination with the Boron-blocking Mo underlayer and the spinel MgAl₂O₄ oxide layer, they have realized giant perpendicular magnetic anisotropy in CoFeB with Hk as high as 17.5–19.5 kOe (x 3 improvement) and Keff as high as 6.9 -9.4 × Merg cm−3 (x 2 improvement). 

Everspin Technologies announced its newest high-reliability additions to the PERSYST MRAM product line: the EM064LX HR and EM128LX HR devices.  These two new xSPI MRAM products are designed for extreme operating environments, with high endurance, temperature performance and data retention. Everspin is targeting aerospace, defense, automotive and high-end industrial applications for these new chips. 

Everspin's new MRAM chips have received an AEC-Q100 Grade 1 qualification for operation from -40°C to +125°C. Each device undergoes a 48-hour burn-in process and provides 10-year data retention at 125°C, ensuring predictable performance even under the most demanding conditions. With 64- and 128-megabit densities achieving 90 Mbytes/sec read and write bandwidth, sustained for over a decade, the EM064LX HR and EM128LX HR are built for systems that cannot risk data loss or degradation.

Everspin Technologies announced its financial results for Q3 2025, with revenues of $14.1 million (up 16% from $12.1 million in Q3 2024), non-GAAP net income of $1.5 million, and a net income of $54,000 (down from $2.3 million last year). At the end of the quarter, Everspin had $45.3 million in cash and equivalents - up $0.3 million in the quarter. 

Everspin says that the strong sales were driven by high demand from its Low Earth Orbital Satellite, Casino Gaming and Energy Management segments. Its data center business remains strong with continued demand for toggle MRAM products for redundant array of independent disks or RAID from a broad selection of data center customers, including Dell, Supermicro, and others.

Frontgrade Technologies announced that it has expanded its MRAM product line, adding two new series, the Dual Quad Serial Peripheral Interface (Dual QSPI) series and the Parallel series. With these new MRAM chips, Frontgrade is targeting aerospace, defense, and industrial applications.

The Dual QSPI series, powered by STT-MRAM, offers a wide range of densities, 128Mb and 1/2/4/8Gb. These new devices bring flash-like non-volatility with SRAM-level speed and endurance. The Dual QSPI interface enables high-speed, synchronous communication and seamless integration into new or existing architectures. These memory chips are designed for boot, configuration, code execution, and data logging.

Researchers from Intel, in collaboration with researchers at Georgia Institute of Technology designed a new SOT-MRAM device at 7 nm. This work spans the entire project range, from device-level characteristics to system-level power performance area. 

Based on ASAP7 PDK design rules, the researchers created the bit-cell and peripheral layouts for SOT-MRAM and designed the entire array. Based on place and route, the system-level PPA was calculated for various memory capacities, demonstrating bit-densities up to 14.8 Mb/mm² and read bandwidths up to 2.98 GB/s. 

Renesas Electronics Corporation introduced two new MCUs, the RA8M2 and RA8D2, both based on 1 Ghz Arm Cortex-M85 processors. Renesas says that these new MCUs deliver an unmatched 7300 Coremarks of raw compute performance, the industry benchmark for MCUs. The optional Cortex-M33 processor enables efficient system partitioning and task segregation.

Both the RA8D2 and RA8M2 offer embedded 1MB high-speed MRAM and 2MB SRAM. SIP options with 4 or 8 MB of external flash in a single package are also available for more demanding applications. 

Researchers at Japan's Kyushu University have developed a new SOT-MRAM memory cell based on thulium iron garnet (TmIG). The researchers say that this material can enhance the efficiency of the memory cell.

The researchers say that TmIG, originally developed in Japan in 2012, is promising, but it requires a very high quality thin film deposition to be used in a memory device. The team has managed to now produce the material in this high quality, using an established mass production method called on-axis sputtering.

Everspin Technologies announced a strategic collaboration with RISC V-based products developer Quintauris, to bring advanced memory solutions into the Quintauris ecosystem.

The two companies will integrate Everspin's MRAM into Quintauris’ reference architectures and real-time platform, with an aim to target automotive, industrial and edge applications where data persistence, integrity, low latency and security are critical.

Renesas Electronics launched a new high-end motor control MCU, the RA8T2. It is based on a 1 GHz Arm Cortex-M85 processor with an optional 250 MHz Arm Cortex-M33 processor, to deliver a high performance level to address real-time control of high-end motors in industrial equipment, robots, and other systems.

The RA8T2 has an integrated 1MB high-speed MRAM, in addition to 2MB SRAM (including 256KB TCM for the Cortex-M85 and 128KB TCM for the M33). The RA8T2 Group MCUs are available now, along with the FSP software.

Researchers from TSMC, Sandford University, ITRI and National Yang Ming Chiao Tung University have fabricate a 64-kb SOT-MRAM based β-phase Tungsten that offers a spin–orbit torque switching of 1 ns, data retention of more than 10 years and a tunnelling magnetoresistance of 146%.

The researchers say that Tungsten is a promising heavy metal for such applications and can generate large spin–orbit torques when stabilized in its β-phase. However, the α-phase, which has a lower spin-Hall angle, is more thermodynamically stable. It is thus challenging to integrate metastable β-tungsten into complementary metal–oxide–semiconductor processes while maintaining phase stability under the back-end-of-line thermal constraints (400 °C for extended durations).