MRAM-Info: the MRAM experts

Researchers from Imec fabricated spin-orbit torque MRAM (SOT-MRAM) devices on 300mm wafers using CMOS compatible processes. The researchers say that these devices offer unlimited endurance, fast switching speeds and low power consumption.

Imec says that SOT-MRAM can overcome the limitation of spin-transfer torque in MRAM memories, but up until now it was only demonstrated in a lab. The core of the SOT-MRAM is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. SOT-MRAM devices feature switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer, unlike STT-MRAM where the current is injected perpendicularly into the magnetic tunnel junction and the read and write operation is performed through the same path.

Researchers from Japan's National Institute of Advanced Industrial Science and Technology (AIST) developed a new process, based on 3D stacking, that forms a single-crystal TMR device on a polycrystal metal wire.

The stacking process creates the TMR thin-film on a single-crystal silicon wafer and then bonds it to a CMOS on another wafer. This opens the way to using these materials in high-performance MRAM devices. The single-crystal TMRs reduces the variation in the device and can enable smaller TMRs. The researcher say that it will take up to 2 years to completely develop the new 3D stacking process.

Everspin announced its financial results for Q1 2018 - revenues reached a record $14.9 million as product revenues grew more than 40% compared to Q1 2017 and as Everspin received an upfront 3D sensor license fee with Alps Electric. Net loss in Q1 was $1.3 million, down from $6.1 million in Q1 2017.

At the end of the quarter, the Everspin had $33.9 million in cash and equivalents (up from $13 million in Q4 2017). In February 2018 Everspin raised $24.5 million in a secondary offering. Everspin expects revenues in Q2 2018 to be in the range of $10.9 million to $11.3 million.

Veeco says that it in the past quarter it has received Ion Beam Etch Solution orders from STT-MRAM developers. Veeco's systems are used for magnetic memory development, and the company is collaborating with a leading semiconductor capital equipment manufacturer in this market.

The company "continues to be encouraged by our customers interest" in the STT-MRAM market.

In 2015, the EU launched the GREAT project, with an aim to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting STT-MTJs to a single baseline technology in the same system on chip. GREAT stands for heteroGeneous integRated magnetic tEchnology using multifonctionnal stAndardized sTack.

After the delivery of a first demonstrator in 2017, the project partners now announced the second hybrid CMOS/MSS-MRAM 180nm Tape Out at Israel-based Tower Jazz. The project partners designed four ICs to validate Analog IP blocks and an ultra-low power MCU comprising a hardware security block.

SMART Modular Technologies announces that it has began shipping its new 1Gb nvNITRO Accelerator Card that features MRAM technology. These new nvNITRO cards use Everspin's STT-MRAM chips. SMART says that nvNITRO is ideally suited for the most demanding transaction logging applications and is designed with plug-and-play capability requiring no changes to system hardware, memory reference, bios or file systems.

SMART further says that the new cards enable a system application to write or log large amounts of data at the full performance of incoming data and provides extremely low and highly consistent read latencies of under 10µs. Because of the non-volatility of the MRAM chips, these cards do not need any power source such as super capacitors or batteries.

Spin Transfer Technologies (STT) announced that its unique Precessional Spin Current (PSC) structure can increase the spin-torque efficiency of any MRAM device by 40-70 percent, which means dramatically higher data retention while consuming less power.

Following advanced testing, the company says that these higher spin-torque efficiencies translate to retention times lengthening by a factor of over 10,000 while reducing write current.