MRAM-Info: the MRAM experts

High-performance STT-MRAM developer Numem announced that it has been selected for a NASA AI project, for which the company will supply its Numem NuRAM MRAM-based Memory. Numem says its memory enables a 2-3x smaller memory area and 20x to 50x lower standby power compared to SRAM.

The project, titled “DNN Radiation Hardened Co-processor as companion chip to NASA’s upcoming High-Performance Spaceflight Computing Processor” will develop a reconfigurable DNN Engine with multiple compute units which can support a wide range of DNN models and frame rates.

Researchers from the National Taiwan University developed an ultra-high performance MTJ, using a superlattice barrier and half-metallic magnets. The so-called superlattice-MTJ can be the basis of a new class of STT-MRAM (which the researcher call SS-MRAM) that achieves ultra-low power RA and write operations, high writing speed and unlimited endurance.

SS-MRAM adopts a superlattice barrier that replaces the MgO layer used in common STT-MRAM. The MgO layer is unstable and also suffers from a very large RA which results in high power consumption for writing operations. The superlattice has higher spin polarization than MgO and so the SS-MARM can provides not only ultra-high MR ratio but also ultra-low RA for high-speed and low power writing.

pMTJ STT-MRAM developer Avalanche Technology announced that its new industrial-grade Serial (SPI) P-SRAM (Persistent SRAM) memory devices are now available. The Serial (SPI) memory devices are designed to be drop-in replacements to Cypress F-RAM and Everspin Toggle MRAM memory products.

The Series (SPI) series supports up to 50MHz clock rate in 1Mb and 4Mb density options, in two packages - 8-pin SOIC and 8-pin WSON. These use Avalanche's 40nm pMTJ STT-MRAM chips.

A team of researchers from the National Tsing Hua University (NTHU) in Taiwan have discovered that by adding a layer of platinum only a few nanometers thick, one can switch the pinned magnetic moments at MRAM cells at will. This was never achieved before, and can lead to faster and more efficient MRAM devices.

The platinum layer is placed between the two layers of the MRAM device - the upper layer, a freely flipping magnet used for data computation and the bottom layer that consists of a fixed magnet, responsible for data storage. Due to spin-orbit interactions, the electric current drives the collective motion of electron spins first. The spin current then switches the pinned magnetic moment effectively and precisely.

SOT-MRAM developer Antaios raised $11 million from VCs and Applied Ventures, to accelerate its next-generation memory development and develop new strategic partnerships.

SOT-MRAM devices feature switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer, unlike STT-MRAM where the current is injected perpendicularly into the magnetic tunnel junction and the read and write operation is performed through the same path.

TSMC announced, during the company's virtual European technology symposium, that it is developing MRAM technologies for its 16nm FinFET platform. The company expects to offer flash-like configuration risk production starting in 4Q21 and RAM-like risk production scheduled for 4Q22.

The company also expects to "explore smaller geometries" for its MRAM (and RRAM) solutions. TSMC started offering 22nm MRAM in 2018.

An international team of researchers led by Israel's Bar Ilan University have developed a new type of MTJ that has four resistance states. The researchers also demonstrated how it is possible to switch between these four different states using spin currents.

The four-state design uses a structure that is in the form of two crossing ellipses instead of one of the standard magnetic layers of the MTJ. Such a design could be used to create multi-level MRAM which stores data more densely compared to current MRAM memories which only have two states in each MTJ.