SOT-MRAM (spin-orbit torque MRAM) has the potential to challenge STT-MRAM, as it is a faster, denser and much more efficient memory technology.
SOT-MRAM devices feature switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer, unlike STT-MRAM where the current is injected perpendicularly into the magnetic tunnel junction and the read and write operation is performed through the same path.
In June 2018, researchers from Imec fabricated SOT-MRAM devices on 300mm wafers using CMOS compatible processes, for the first time.
Hprobe announced a new magnetic test head for MRAM Wafer Sort. The new module, the H3DM-XL, is at the heart of the latest addition to Hprobe’s IBEX line, the IBEX-WS.
The IBEX-WS test equipment integrates 3D magnetic field capabilities, while increasing field area and uniformity for wafer probing large MRAM arrays. It also features a unique patented robotized 3D Field Calibration Unit (FCU) for high-speed field mapping and monitoring.
Researchers at Taiwan's Semiconductor Research Institute (TSRI) unveiled a new SOT-MRAM memory device that they developed in collaboration with University scientists.
The new device uses a perpendicular magnetic anisotropy (PMA) technique. According to the TSRI researchers, they are the second team to successfully produce MRAM chips based on PMA (Intel is the first team to have achieved this).
Researchers from Northwestern University, in collaboration with researchers from China, Italy and France, developed a new SOT-MRAM device structure that enables deterministic switching without any need for bias magnetic fields.
The new approach, unlike most earlier methods, can be scaled to large wafers with good uniformity, since it doesn't rely on having a structural asymmetry in the device. SOT-MRAM devices based on this structure could be faster and more energy-efficient than current designs.
Integral Solutions International (ISI) announced its first shipment of a commercial SOT-MRAM tester system. This new equipment was developed by integrating a commercial pulser with ISI’s proprietary bias-tee and measurement electronics.
ISI says that the new tester system generates pulses as narrow as 300pS, suitable for R&D applications which require extremely narrow pulse widths. In parallel, ISI is also developing its proprietary Gen-4 Pulser System, which will provide high-throughput and cost-effective measurement solutions with the flexibility of testing either STT-MRAM or SOT-MRAM devices. The Gen-4 system is expected to be released in the fall of 2021.
Researchers from Seoul's National University and Pohang's University of Science and Technology (POSTECH) report that a 2D iron germanium telluride (Fe3GeTe2, or FGT) layer is an excellent candidate to be used as the basis SOT-MRAM material.
An SOT-MRAM based on FGT is highly energy-efficient, in fact the researchers say that the measured magnitude of SOT per applied current density is two orders of magnitude larger than the values reported previously for other candidate materials.
SOT-MRAM developer Antaios raised $11 million from VCs and Applied Ventures, to accelerate its next-generation memory development and develop new strategic partnerships.
SOT-MRAM devices feature switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer, unlike STT-MRAM where the current is injected perpendicularly into the magnetic tunnel junction and the read and write operation is performed through the same path.
Digitimes reports that Taiwan's Industrial Technology Research Institute (ITRI) has been developing spin-orbit torque MRAM (SOT-MRAM) for many years, and is now transferring this technology to local chipmakers in Taiwan.
According to Digitimes , ITRI has established a platform for its SOT-MRAM technology certification and trial runs on 8-inch wafers. The report does not detail which companies are licensing ITRI's technology.
Researchers from National Taiwan University demonstrate that chalcogenide material BiTe with non-epitaxial structure can give rise to a giant spin Hall ratio and SOT efficiency (~ 200%) without obvious evidence of topologically-protected surface state (TSS).
The researchers explain that a clear thickness-dependent increase of the SOT efficiency indicates that the origin of this effect is from the bulk spin-orbit interaction of such materials system. Efficient current-induced switching through SOT is also demonstrated with a low zero-thermal critical switching current density (~ 6×105 A/cm2).
Researchers at Tohoku University demonstrated a high-speed spin-orbit-torque MRAM (SOT-MRAM) memory cell compatible with 300 mm Si CMOS technology.
The SOT device achieved high-speed switching (down to 0.35 ns) and a high thermal stability factor (E/kBT 70) which the researchers say is sufficient for high speed non-volatile memory applications. The device can withstand annealing at 400°C. The researchers used these devices to create a complete SOT-MRAM memory cell.
Hprobe, a developer of testing equipment for magnetic devices, announced that it has teamed up with the IMEC research institute to jointly extend Hprobe's fast testing protocols for SOT-MRAM devices.
Hprobe has already begun to optimize its test flow for SOT-MRAM devices in order to bring the characterization and testing to an industrial level with the primary objective to reduce the testing time while maximizing yield.