Article last updated on: Apr 04, 2019

SOT-MRAM (spin-orbit torque MRAM) has the potential to challenge STT-MRAM, as it is a faster, denser and much more efficient memory technology.

SOT-MRAM devices feature switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer, unlike STT-MRAM where the current is injected perpendicularly into the magnetic tunnel junction and the read and write operation is performed through the same path.

In June 2018, researchers from Imec fabricated SOT-MRAM devices on 300mm wafers using CMOS compatible processes, for the first time.

The latest SOT-MRAM news

Researchers demonstrate that chalcogenide materials can be highly suitable for SOT-MRAM

Researchers from National Taiwan University demonstrate that chalcogenide material BiTe with non-epitaxial structure can give rise to a giant spin Hall ratio and SOT efficiency (~ 200%) without obvious evidence of topologically-protected surface state (TSS).

BiTe material system for SOT-MRAM schema (NUS)

The researchers explain that a clear thickness-dependent increase of the SOT efficiency indicates that the origin of this effect is from the bulk spin-orbit interaction of such materials system. Efficient current-induced switching through SOT is also demonstrated with a low zero-thermal critical switching current density (~ 6×105 A/cm2).

Researchers in Japan developed a high-speed SOT-MRAM memory cell compatible with 300mm Si CMOS technology

Researchers at Tohoku University demonstrated a high-speed spin-orbit-torque MRAM (SOT-MRAM) memory cell compatible with 300 mm Si CMOS technology.

The SOT device achieved high-speed switching (down to 0.35 ns) and a high thermal stability factor (E/kBT 70) which the researchers say is sufficient for high speed non-volatile memory applications. The device can withstand annealing at 400°C. The researchers used these devices to create a complete SOT-MRAM memory cell.

Hprobe teams up with IMEC to develop SOT-MRAM testing tools

Hprobe, a developer of testing equipment for magnetic devices, announced that it has teamed up with the IMEC research institute to jointly extend Hprobe's fast testing protocols for SOT-MRAM devices.

Hprobe wafer prober system photo

Hprobe has already begun to optimize its test flow for SOT-MRAM devices in order to bring the characterization and testing to an industrial level with the primary objective to reduce the testing time while maximizing yield.

NTHU researchers manage to manipulate exchange bias by spin-orbit torque

Researchers from Taiwan's National Tsing Hua University (NTHU)managed to use a spin current to manipulate the exchange bias in Spin-Orbit Torque memory (SOT-MRAM). The researchers say that this has been a long-time challenge in the field.

MRAM chip Manipulating exchange bias by spin-orbit torque (NTHU)

To achieve this, the researchers added a platinum layer under the ferromagnetic and antiferromagnetic layers of the MRAM device. The researchers patented this technique before publishing their findings.

New material could finally enable fast, efficient and dense SOT-MRAM devices

SOT-MRAM (spin-orbit torque MRAM) has the potential to challenge STT-MRAM, as it is a faster, denser and much more efficient memory technology. Up until now, though, no suitable material that features both high electrical conductivity and a high spin hall effect was developed.

Now researchers at the Tokyo Institute of Technology have developed a new thin film material made from bismuth-antimony (BiSb) that is a topological insulator that simultaneously achieves a colossal spin Hall effect and high electrical conductivity - which means it could be used to create SOT-devices.

Imec researchers deposited SOT-MRAM devices on 300 mm wafers

Researchers from Imec fabricated spin-orbit torque MRAM (SOT-MRAM) devices on 300mm wafers using CMOS compatible processes. The researchers say that these devices offer unlimited endurance, fast switching speeds and low power consumption.

Imec says that SOT-MRAM can overcome the limitation of spin-transfer torque in MRAM memories, but up until now it was only demonstrated in a lab. The core of the SOT-MRAM is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. SOT-MRAM devices feature switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer, unlike STT-MRAM where the current is injected perpendicularly into the magnetic tunnel junction and the read and write operation is performed through the same path.