Toshiba has developed a prototype memory element for STT-MRAM that (according to Toshiba) achieves the world's lowest power consumption yet reported. STT-MRAM based on this element has the potential to surpass the power consumption efficiency of SRAM as cache memory.

Toshiba's improved structure is based on perpendicular magnetization and takes element miniaturization to below 30nm. Introduction of this newly designed "normally-off" memory circuit with no passes for current to leak into cuts leak current to zero in both operation and standby without any specific power supply management. The company says it improved the speed of their previous design - while reducing the power consumption by 90%.

Back in June 2010 We learned that Qualcomm is developing MRAM technologies. Now Qualcomm's QTI Advanced Memory Team posted a job opening that details a mobile STT-MRAM lead technologist - that will lead the development of next-generation mobile SOC memory subsystems that integrate Perpendicular STT-MRAM.

Spingate announced that they invented a multi-bit Spin-RAM, which can store two bits per MTJ. It uses magnetic materials with perpendicular anisotropy and has a cell size of 4F², which is the smallest currently reported in the industry. This kind of memory can provide a density of about 160 Gbits/in² (0.257 Gbit/mm²) at 45 nm. They say their design has excellent thermal stability, and so can scale down to 10 nm.

Spingate's Spin-RAM uses the company's proprietary hybrid write mechanism based on a simultaneous application of a spin-polarized current and a bias magnetic field. The hybrid write mechanism provides the Spin RAM with a high switching speed (about 1 ns or less), low density of the spin-polarized current (about 10⁶ A/cm² or less), excellent endurance (about 10¹⁵ or above) and error rate. Spingate says that it can be smoothly arranged in a 3D architecture (without additional layers or selection transistors), and 1 Tbits/in² can be achieved at 25 nm (with only two layers of MTJ) or at 18 nm (in a 2D architecture).

MicroSense says that they see an increase in orders for its MRAM magnetic metrology systems. MicroSense's metrology tools characterize the magnetic properties of multi-layer wafers used in the development and manufacturing of perpendicular MRAM. They offer a 300mm Polar Kerr (out-of-plane) MRAM metrology system, the KerrMapper (in-plane) tool and Vibrating Sample Magnetometers (VSM) for MRAM makers.

The company has been selling Gen-1 MRAM metrology tools since 2004. They say that now, with the recent developments in STT-MRAM, they see a number of new MRAM tool orders.

Samsung developed a perpendicular MTJ element using 17nm technology - the world's smallest. This paves the way towards sub-20nm STT-MRAM. Up until now it was believed that to create such a small P-MTJ you will have to use a multi-layer structure and a rare-earth material for the ferromagnetic electrode. Samsung however used regular materials and structure (Ta/CoFeB/MgO/Ta) and optimized the oxidation process for the tunnel insulator (MgO).

By increasing the anisotropic energy on the joint interface the perpendicular magnetization of the ferromagnetic electrode was stabilized. Samsung reports a thermal stability factor of 34, a TMR ratio of 70% and a writing current of 44microampere with a perpendicular magnetization MTJ element whose cross-section area is 17 x 40nm. There is still room for improvement in the thermal stability factor in order to achieve over 1Gbit capacity at 20nm. This can be realized by making more improvements to the newly developed oxidation process for the tunnel insulator

Toshiba says that their newly developed perpendicular magnetization-type magnetic tunnel junction (MTJ) device has excellent properties - and it can be a basic element towards a gigabit STT-MRAM device. The company says that these 'research results' are encouraging and they will now shift to the development of products. Commercialization of gigabit STT-MRAM is expected within 3 to 4 years.

MTJ cross section (Toshiba)

The device's writing current density is 5 x 10⁵Acm^-2, which is 1/6 that of the company's existing products. And its magnetic resistance (MR), which determines data reading margin, is 200%, which was drastically improved from the 15% of the existing products. Toshiba managed to have both a low writing current density and a high MR ratio by using cobalt and iron based materials for the recording layer.

Spingate is a US-based company focusing on perpendicular MRAM technologies. In November 2009 we have talked to Dr. Alex Shukh, Spingate's co-founder, CTO and CEO, and he explains Spingate's technology . Today Spingate sent us another update.

Spingate says that since 2009 they continued to build their IP portfolio. The company invented and has been developing a new class of nonvolatile spin logic that combines advantages of conventional CMOS logic and MRAM technologies. Spingate's spin logic represents an elegant synthesis of the conventional logic with embedded MRAM cells residing above the silicon. The memory cells have a marginal impact on layout of the logic but provides it with a non-volatility. The spin logic may offer significant performance enhancements of conventional logic devices by eliminating numerous off-chip data flows resulting in speeding up the entire system. The embedded MRAM cells employ spin induced switching mechanism and magnetic materials with either in-plane or perpendicular anisotropy. The spin logic employing perpendicular magnetic materials has better scalability and lower switching current than that based on in-plane materials. The company's logic is especially attractive for application in field programmable gate arrays (FPGAs) due to its non-volatility, simplicity, high speed and reduced chip size. Moreover it can be used for creation of nonvolatile micro-controllers and microprocessors.

During the International Electron Device Meeting (IEDM) exhibition we got some updates about STT-MRAM research done at IBM, Samsung and Hynix-Grandis (who are researching STT-MRAM together).

IBM is working together with TDK and has presented a new 4-kbit perpendicular STT-MRAM array using tunnel junctions. Samsung has presented an on-axis MRAM with a novel MTJ, which they say open he way towards sub-30nm scaling. Using ferromagnetic electrode and a different MTJ structure design, Samsung think that they can scale this to a sub-20nm level.

Researchers from Japan's AIST institute have developed a new Tunnel-Magnetoresistance (or TMR) element with a low data writing current and high data stability. This kind of TMR is required for high-capacity MRAM. In fact the team says that this TMR can be used to make perpendicular STT-MRAM with densities of over 10GBit.

With existing TMRs, there's a trade-off between data writing current and data stability. Data loss happens if the free-layer's magnetization is reversed because of thermal agitation, and if you make a thicker free-layer it solves the data-loss issues, but you need more current. The new design solved this issue by using a free layer that is made from a nonmagnetic layer between two ferromagnetic layers. The resistance to thermal agitation is improved - it is five times better, while the current is only increased by 80%.

The team used an in-plane magnetization film for the free layer, which can be used to make a 1-Gbit MRAM. They plan to make the current even lower with a perpendicular magnetization film, which will allow for a 10 Gbit MRAM device.

Spingate is a new US-based fabless company focusing on development, licensing and manufacturing of solid state memory, specifically, perpendicular MRAM.

We have talked to Dr. Alex Shukh, Spingate's co-founder, CTO and CEO. Alex explains that they have decided to focus on perpendicular MRAM because according to their estimates it does not suffer from several fundamental issues of its longitudinal (in-plane) analogue.

However, to be successful with p-MRAM development, Spingate needs to solve several serious problems, such as, a reduction of energy consumption during writing, development of new magnetic materials with perpendicular anisotropy for storage and reference layers exhibiting high GMR, etc.

Spingate's IP portfolio already includes one granted and several pending patents on p-MRAM, which covers multi-bit cell, 3D-memory designs, etc. The proposed solutions should close existing cell density gap between MRAM and Flash since 2D-Flash won't be able to compete with 3D-MRAM. Spingate are currently working on cell design development and optimization, and is looking for investors.