June 2010

Hitachi and Tohoku University have developed n STT-RAM that can be written using multi-level cell (MLC) technology. They actually call their technology SPRAM (spin-transfer torque memory).

The idea is to three-dimensionally stack two TMR elements and connect them in series. This creates , four-value memory (2 bits per cell). Hitachi has already produced a prototype of this memory. The biggest advantage of the MLC SPRAM is that it can reduce bit costs in proportion to the number of stacked TMR elements, Hitachi said. For example, when two TMR elements are stacked, bit costs are reduced by about half.

The US Defense Advanced Research Projects Agency (DARPA) has awarded Grandis with a $8.6 million 2nd phase project for STT-RAM chip development. The first phase ($6.0) was received in October 2008.

Phase 2 will focus on test of verification of STT-RAM integrated memory arrays.

Fujitsu Laboratories has developed a new memory cell circuit for STT-MRAM that reverses the typical order of magnetic tunnel junctions (MTJ) to enable a space savings of 60% and achieve a greater degree of integration

The memory cell circuit in spin-torque-transfer MRAM is a circuit that connects the MTJ element with a cell-select transistor, which act as switches that select which MTJ elements to write to or read from. With existing memory cell circuits, when the MTJ element of a spin-torque-transfer MRAM has been written to a high-resistance state ("1"), voltage is lowered through variable resistance - this requires a larger current to write than when an MTJ element it is switched to a low resistance state ("0"), which is not affected by variable resistance. In other words, because the cell-select transistor's current-driving capability is low, writing to a high-resistance state ("1") would require a significant current. As such, even with a low driving-current capability, cell-select transistors need to be relatively large to ensure an adequate write current, which has been a barrier to reducing transistor size.

There are reports that Hitachi might spin-off their STT-MRAM business. Hitachi calls this technology SPRAM, and plans to devise a 16- and 64-Mbit device in 2012, and a 256-Mbit and 1-Gbit chip by 2015.

Menta SAS and LIRMM (The Montpellier Laboratory of Informatics, Robotics, and Microelectronics) has confirmed the tape out of world’s first MRAM-based FPGA. The FPGA is based on Menta's eFGPA Core programmable logic architecture and on CEA-LETI and Crocus's MRAM technology. It is manufactured in CMOS 130nm with magnetic junction in 120nm and provides capacity of 1,444 LUT4, equivalent to approximately 20K logic gates.

Pr Lionel Torres, in charge of the MRAM design project at LIRMM, says that “MRAM-based FPGA proposes better versatility with partial or dynamic re-configurability capabilities, instant on/off total or partial energy saving”.