The latest Fujitsu news:
Fujitsu Laboratories has developed a new memory cell circuit for STT-MRAM that reverses the typical order of magnetic tunnel junctions (MTJ) to enable a space savings of 60% and achieve a greater degree of integration
The memory cell circuit in spin-torque-transfer MRAM is a circuit that connects the MTJ element with a cell-select transistor, which act as switches that select which MTJ elements to write to or read from. With existing memory cell circuits, when the MTJ element of a spin-torque-transfer MRAM has been written to a high-resistance state ("1"), voltage is lowered through variable resistance - this requires a larger current to write than when an MTJ element it is switched to a low resistance state ("0"), which is not affected by variable resistance. In other words, because the cell-select transistor's current-driving capability is low, writing to a high-resistance state ("1") would require a significant current. As such, even with a low driving-current capability, cell-select transistors need to be relatively large to ensure an adequate write current, which has been a barrier to reducing transistor size.
Fujitsu Laboratories and the University of Toronto announced that they have jointly developed the world's first high-reliability read-method for use with spin-torque-transfer (STT) MRAM that is insusceptible to erroneous writes.
The newly developed read-method uses a negative resistance that is intermediate between the MTJ's high resistance and low resistance on a parallel circuit. If the MTJ is in a high-resistance state, this circuit exhibits negative-resistance characteristics. If the MTJ is in a low-resistance state, then it exhibits normal-resistance characteristics. These characteristics allow the resistance value to be read at lower voltages than before, suppressing the tendency of the read operation to reverse the direction of magnetization and avoiding the problem of erroneous write operations.
Fujitsu Laboratories and the University of Toronto plan to continue with R&D related to STT MRAM to strive toward practical implementation, such as lowering write currents and developing process technologies for further miniaturization.
Fujitsu's MB85R2001 and MB85R2002 feature non-volatile memory with high-speed data writing, low power consumption and the ability to provide a large number of write cycles.
The MB85R2001 and MB85R2002 FRAM chips are ideal for automotive navigation systems, multifunction printers, measuring instruments and other advanced applications that can use non-volatile memory to store various parameters, record equipment operating conditions and preserve security information.
The configuration of MB85R2001 is 256K words x 8bits, while the configuration of MB85R2002 is 128K words x 16 bits. Both MB85R2001 and MB85R2002 feature read access times of 100ns and read/write cycle times of 150ns. The MB85R2001 and MB85R2002 operate from 3V to 3.6V.
Fujitsu today announced the availability of its 2 Mbit Ferroelectric RAM (FRAM or FeRAM) memory chips, which the company claims is the largest capacity FRAM in volume production in the world. The memory product have the same electrical characteristics and use the same TSOP-48 package as Fujitsu's 1 Mbit FRAM products, equating to double the capacity over previous chips. Sampling price of the chips is set at 2,000 Yen ($16.91 USD).
Seiko Epson Corp and Fujitsu have announced the results of their joint project to develop next-generation ferrorelectric random access memory (FRAM) technology. The joint development project was successfully completed recently and produced the anticipated results.
Through the project, the two companies developed technology for forming, processing and evaluating a new ferroelectric (PZT) film and created FRAM memory core process technology that is highly integrated (four times the level of conventional FRAM), features high performance (read/write speeds over three times faster than conventional FRAM) and offers a high degree of reliability (capable of more than 100 trillion read/write cycles). FRAM is currently attracting attention as a technology for secure memory, and this level of performance is claimed to be a world first. Since the ferroelectric process can be added to existing CMOS logic processes, it will be suitable for the development of mass production technologies.
MRAM has been considered as a potential next-gen memory technology for quite some time, and it was in the spotlight at the VLSI 2005 symposium. NEC and Toshiba jointly unveiled a new Toggle MRAM cell structure in which the magnetic tunnel junction has a multi-layered structured.
Fujitsu Laboratories presented a new approach to MRAM circuity. The company is developing embedded MRAM and they have now proposed a one-transistor/two-magnetic tunnel junction (1T/2MTJ) structure MRAM cell with a direct voltage-sensing scheme, which it said has the advantages of DRAMs. In the proposed 1T/2MTJ cell, two MTJs were connected in series. Fujitsu fabricated the test device with each MTJ measuring 0.2 x 0.4 micron and confirmed the cell operation.