Grandis announced that it has been awarded $6.0 million from the Defense Advanced Research Projects Agency (DARPA) for the initial phase of research to develop spin-transfer torque random access memory (STT-RAM) chips (for the 45 nm technology node and beyond). The total value of the effort, if all phases of the development program are completed, could be up to $14.7 million over four years.
The program will be carried out by a world-class collaboration between Grandis and the Universities of Virginia and Alabama. Under the direction of Principal Investigator Dr. Eugene Chen of Grandis, development work will cover STT materials and processes, STT architecture and circuit blocks, and ultimately test and verification of STT-RAM integrated memory arrays.
"The goal of this program is to deliver dense, high-performance, cost-effective universal memory chips employing STT technology," explained Dr. Devanand Shenoy, program manager in DARPA's Microsystems Technology Office. "Demanding specifications must be met by the materials and devices throughout the project to ensure delivery of ground-breaking technology."