Fujitsu Laboratories has developed a new memory cell circuit for STT-MRAM that reverses the typical order of magnetic tunnel junctions (MTJ) to enable a space savings of 60% and achieve a greater degree of integration
The memory cell circuit in spin-torque-transfer MRAM is a circuit that connects the MTJ element with a cell-select transistor, which act as switches that select which MTJ elements to write to or read from. With existing memory cell circuits, when the MTJ element of a spin-torque-transfer MRAM has been written to a high-resistance state ("1"), voltage is lowered through variable resistance - this requires a larger current to write than when an MTJ element it is switched to a low resistance state ("0"), which is not affected by variable resistance. In other words, because the cell-select transistor's current-driving capability is low, writing to a high-resistance state ("1") would require a significant current. As such, even with a low driving-current capability, cell-select transistors need to be relatively large to ensure an adequate write current, which has been a barrier to reducing transistor size.
Fujitsu Laboratories has reversed the order of the MTJ element's magnetic layers, enabling the development of a new MTJ element with a top-pinned structure - that differs from previous structures - that consists of a pinned layer, tunnel barrier, and free layer. However, because the distance between the tunnel barrier of the top-pinned MTJ element and its bottom electrode has been reduced, electrical short failures are more likely to occur during fabrication - as a countermeasure to address this issue, Fujitsu Laboratories has inserted a buffer layer to maintain separation between the tunnel barrier and bottom electrode, which allows the output from the low-resistance ("0") writing to travel in the same direction as the cell-select transistor's low driving-current capacity, thus making it possible for the cell-select transistor to still function at a smaller size.