NEC Corporation today announced that it has succeeded in developing new MRAM cell technology suitable for high speed memory macro embedded in next generation system LSIs. The newly developed cell technology includes three key elements; a 2T1MTJ (two transistors and one magnetoresistive tunneling junction) cell structure to accelerate write mode cycle time, a 5T2MTJ cell structure to accelerate read mode cycle time and a write-line-inserted MTJ to reduce write current. The new cell technology realizes added-value, non-volatile MRAM macros that can be substituted for SRAM (static random access memory) macros embedded in system LSIs.
Features of the newly developed elements:
1. 200MHz random access write operation: Elimination of the upper limit of the writing current by a 2T1MTJ cell enables high speed write operation. In conventional MRAM memory cells, writing current must be within upper and lower limits (note 1). This complicates the write current source circuit and it thus cannot operate at over 100MHz.
2. 500MHz random access read operation: Intra-cell-signal amplification in a 5T2MTJ cell enables high speed read operation. Cell current signal is amplified and transformed into voltage signal in each cell. In conventional MRAM memory cells, a small reading current difference signal through the bit line with large parasitic capacitance makes sense amplifier circuits complicated. These kinds of circuits cannot operate at over 200MHz.
3. Reduction of writing current down to 1/3: A write-line-inserted MTJ structure reduces writing current to 1/3 as compared with conventional MTJ structure writing currents. This small current reduces MRAM cell size.
Posted: Jul 14,2006 by Ron Mertens