Technical / Research

Researchers from Beihang University and Truth Memory Corporation have fabricated a 1 Kbit SOT-MRAM chip using a 180 nm complementary metal oxide semiconductor (CMOS) process, and implemented a physical unclonable function (PUF) on it. This research represents a significant step forward in the field of PUFs.

The newly developed SOT-MRAM sr-PUF achieves a strong, highly reliable, and reconfigurable PUF that can resist machine-learning attacks. The performance of the SOT-MRAM sr-PUF is remarkable - it has a challenge-response pair (CRP) capacity of 109. Its uniformity is 50.07%, diffuseness is 50%, uniqueness is 49.89%, and the bit error rate is 0%, even in a 375 K environment. These values are near-ideal, indicating excellent randomness and reliability.

Researchers from the Johannes Gutenberg University Mainz (JGU) in Germany, in collaboration with Antaios, have developed a new SOT-MRAM based platform that enables highly efficient and powerful data processing and storage.

By exploiting previously neglected orbital currents, the researchers have developed a unique magnetic material incorporating elements such as Ruthenium as a SOT channel—a fundamental building block of SOT MRAM—to significantly enhance performance. 

The Virginia Innovation Partnership Corporation (VIPC) has awarded $100,000 to Virginia Commonwealth University (VCU) to expand the MRAM research conducted by Dr. Jayasimha Atulasimha

Atulasimha’s group is developing skyrmion-mediated MRAM (SkMRAM), a nanomagnet-based RAM technique that builds upon STT-MRAM technology while significantly improving energy efficiency. By adding a layer of heavy metal to STT-MRAM, energy consumption is reduced by 100-1000x, or 2-3 orders of magnitude. The resulting product is non-volatile, meaning that it can retain data even when the device is powered off, and has a very low write-errors rate, which means that it saves energy while writing information. It also doesn’t require standby power to retain information and is reliable. One patent currently covers this technology.

Researchers from Osaka University developed a new MRAM device architecture that enables an electric-field-based writing scheme with reduced energy consumption compared to the present current-based approach.

The researchers have developed a new component for electric field control of MRAM devices, with the key innovation being a multiferroic heterostructure with magnetization vectors that can be switched by an electric field. The researchers also demonstrate that two different magnetic states can be reliably realized at zero electric field by changing the sweeping operation of the electric field. This means a non-volatile binary state can be intentionally achieved at zero electric field.

Researchers from Korea's Ulsan National Institute of Science & Technology (UNIST) have designed a new MRAM structure, based on graphene, that offers higher efficiency (and lower heat generation) compared to existing MRAM solutions.

The design of the MRAM device is based on a graphene layer sandwiched between a magnetic insulator (yttrium iron garnet) and a ferroelectric material (PVDF-TrFE). Upon application of a voltage pulse, the current flow through the graphene is altered, enabling the storage of binary data based on this current direction.

Hprobe, a developer of testing equipment for magnetic devices, announced a strategic collaboration with NY CREATES, a lab-to-fab bridge for advanced electronics, to advance testing capabilities for next-generation semiconductor memory technologies. This joint development project will focus on the co-development of advanced testing equipment at the 300mm wafer scale.

NY CREATES and Hprobe will work together to support new testing solutions for MRAM, RRAM and selector devices. The joint project will focus on initial testing of MRAM and RRAM wafers from NY CREATES using Hprobe’s equipment, including the full-scale implementation of Hprobe’s IBEX wafer-level magnetic tester. Development of breakthrough testing procedures and algorithms for MRAM, RRAM, and selector devices, will also seek to advance the state-of-the-art in semiconductor memory testing.

Kioxia Corporation (Toshiba's memory unit that was spun-off in 2021), in collaboration with SK Hynix, announced that it has developed the world's smallest 1Selector-1MTJ cell.

Kioxia says that the two companies have demonstrated a reliable 1 selector-1 MTJ (1S1M) cell read/write operation with low read disturb rate of <1E^-6 in 64 Gb cross-point array architecture. They have implemented cross-point 1S1M chips integrated in Half Pitch (HP) of 20.5 nm and MTJ CD of 20 nm using As-doped SiO2 selector and perpendicularly magnetized MTJ (p-MTJ).

Researchers from  Purdue University were awarded with a new project to advanced AI using research performed at Purdue for over a decade. The CHEETA:CMOS+MRAM project will utilize a CMOS+X approach specifically leveraging the unique capabilities of MRAM memory to design efficient in-memory computing hardware fabrics.

The CHEETA project aims to deliver impactful improvements in energy efficiency and sensor-to-decision latency compared to the current commercial standard. The project received funding from the Applied Research Institute. 

Researchers from the Institute of Science Tokyo (formerly Tokyo Tech), in collaboration with Western Digital, has developed a new high-performance material suitable for low-power SOT-MRAM.

The researchers are using BiSb material under the CoFeB/MgO, with perpendicular magnetic anisotropy. By optimizing the interfacial layer thickness as well as deposition condition of BiSb, the researchers managed to achieve a large effective spin Hall angle and relatively high electrical conductivity. The researchers continued to demonstrate spin–orbit torque-induced magnetization switching driven by a small threshold current density.