Technical / Research

Researchers from the University of Texas at Austin, together with TSMC, have produced 300 mm-compatible SOT-MRAM devices and have shown SOT-MRAM is uniquely effective candidate for implementation of crossbar accelerators in memory- and energy-limited applications such as AI.

The SOT-MRAM devices offer 150% tunnel magnetoresistance (TMR) ratio, fast (2 ns) and low voltage (<1 V) operation, low energy dissipation (2 pJ), low write noise (0.1%), and low device-to-device variation of 10%. 

Researchers from Beihang University, Aix-Marseille University and Université Paris-Saclay, in collaboration with Truth Memory Corporation, demonstrated a highly efficient orbital torque-driven magnetic tunnel junction (MTJ).

The researchers say that in standard SOT-MRAM devices, the β-phase tungsten (β-W) write electrodes suffer from high electrical resistance and strict thickness limitations. To overcome both issues, the researchers harnessed the hidden degree of freedom, the orbital angular momentum. 

Avalanche Technology announced that has achieved the phase-one milestone of its magnetic cell scaling project, as it aims to be able to produce higher-density space-grade MRAM. This cell size reduction, in concert with additional planned geometry shrink, will enable the increase in memory density by 16X.

Avalanche has successfully established high density MTJ array manufacturing in a high volume production environment at 22 nm process node, achieving an MTJ critical dimension (CD) of 40 nm with a pitch of 100nm and below. Avalanche says that through rigorous optimization of MTJ hard mask and etch processes, the dense array delivers low bit error rates, enabling a minimum cell size of 0.01 μm² and high yield, gigabit class monolithic chip production, with demonstrated scalability to 12 nm process nodes.

Researchers from the Institute of Science Tokyo (formerly Tokyo Tech), in collaboration with Western Digital, developed a new MRAM free layer with a giant perpendicular magnetic anisotropy, with the potential scaling to CMOS 5 nm process. This is said to be the most advanced MRAM free layer to date.

The researchers explain that by using the Boron-rich Co₁₉Fe₅₆B₂₅ layer in combination with the Boron-blocking Mo underlayer and the spinel MgAl₂O₄ oxide layer, they have realized giant perpendicular magnetic anisotropy in CoFeB with Hk as high as 17.5–19.5 kOe (x 3 improvement) and Keff as high as 6.9 -9.4 × Merg cm−3 (x 2 improvement). 

Researchers at Japan's Kyushu University have developed a new SOT-MRAM memory cell based on thulium iron garnet (TmIG). The researchers say that this material can enhance the efficiency of the memory cell.

The researchers say that TmIG, originally developed in Japan in 2012, is promising, but it requires a very high quality thin film deposition to be used in a memory device. The team has managed to now produce the material in this high quality, using an established mass production method called on-axis sputtering.

Researchers from TSMC, Sandford University, ITRI and National Yang Ming Chiao Tung University have fabricate a 64-kb SOT-MRAM based β-phase Tungsten that offers a spin–orbit torque switching of 1 ns, data retention of more than 10 years and a tunnelling magnetoresistance of 146%.

The researchers say that Tungsten is a promising heavy metal for such applications and can generate large spin–orbit torques when stabilized in its β-phase. However, the α-phase, which has a lower spin-Hall angle, is more thermodynamically stable. It is thus challenging to integrate metastable β-tungsten into complementary metal–oxide–semiconductor processes while maintaining phase stability under the back-end-of-line thermal constraints (400 °C for extended durations). 

TSMC is launching its first design center in Europe, with a focus on memory technologies for automotive applications. The company announced that it will start developing 5nm MRAM technologies, to complement its 22-nm (in production), 16-nm (ready for customers verification) and 12-nm (already in development) technologies. 

Scaling MRAM technology to 5nm will be a significant step, required, according to TSMC, to implement AI automotive chips and technologies. The company will also develop 6 nm RRAM memory in the new design center.

A team of researchers at Tohoku University have achieved the world's lowest write power SOT-MRAM device, that is also offering an extremely fast write time.

The researchers focused on the tilt angle of the canted SOT device and the magnetic anisotropy of the free layer, using micro-magnetic simulation to reduce the write power. The have achieved a write power of 156 fJ in 75° canted SOT devices fabricated using a 300mm wafer process. 

Researchers from Beihang University and Truth Memory Corporation have fabricated a 1 Kbit SOT-MRAM chip using a 180 nm complementary metal oxide semiconductor (CMOS) process, and implemented a physical unclonable function (PUF) on it. This research represents a significant step forward in the field of PUFs.

The newly developed SOT-MRAM sr-PUF achieves a strong, highly reliable, and reconfigurable PUF that can resist machine-learning attacks. The performance of the SOT-MRAM sr-PUF is remarkable - it has a challenge-response pair (CRP) capacity of 109. Its uniformity is 50.07%, diffuseness is 50%, uniqueness is 49.89%, and the bit error rate is 0%, even in a 375 K environment. These values are near-ideal, indicating excellent randomness and reliability.

Researchers from the Johannes Gutenberg University Mainz (JGU) in Germany, in collaboration with Antaios, have developed a new SOT-MRAM based platform that enables highly efficient and powerful data processing and storage.

By exploiting previously neglected orbital currents, the researchers have developed a unique magnetic material incorporating elements such as Ruthenium as a SOT channel—a fundamental building block of SOT MRAM—to significantly enhance performance.