Tohoku University researchers develop the world's fastest STT-MRAM

Researchers from Japan's Tohoku University developed a 128 Mb STT-MRAM device that features a write speed of 14 nm, the world's fastest STT-MRAM chip at a density over 100 Mb.

Tohoku 128 MB STT-MRAM 14 ns write speed image

To achieve this high speed, the researchers developed MTJs that are integrated with CMOS, which also significantly reduces the power-consumption of the memory device.

Gyrfalcon's new AI chip first to use TSMC's embedded MRAM

In June 2017 it was reported that Taiwan Semiconductor Manufacturing Company (TSMC) will start producing embedded MRAM in 2018 using a 22 nm process. In what may bet he first adoption of TSMC's eMRAM technology, AI accelerator startup Gyrfalcon Technology announced the commercial availability of its LightSpeeur 2802M, AI ASIC that include TSMC's eMRAM.

The 2802M ASIC has 40MB of eMRAM memory, which can support large AI models or multiple AI models within a single chip. Applications include image classification, voice identification, voice commands, facial recognition, pattern recognition and more.

Yole Developpement sees STT-MRAM leading the embedded emerging-NVM market

Market analyst firm Yole Developpement presents its latest next-generation memory forecasts in an interesting new article. The company says that following more than 15 years of development, PCM is finally taking off in stand-alone applications due to strong support from Intel and Micron.

Emerging NVM market (2018-2023, Yole)

STT-MRAM is expected to lead the embedded memory race as many foundries are rushing to add MRAM support and expertise to their product lines. STT-MRAM is promising for enterprise storage SCM.

IMEC: STT-MRAM is suitable for 5 nm last level cache, offers significant energy gains over SRAM in large memory densities

Researchers at Belgium-based research institute Imec presented the first power-performance area comparison between SRAM and STT-MRAM last-level cache at the 5 nm node.

The analysis, based on design-technology co-optimization and silicon verified models, reveals that STT-MRAM meets the performance requirements for last-level caches in the high-performance computing domain. For larger memory densities, STT-MRAM was found to offer significant energy gains compared to SRAM.