Researchers at Belgium-based research institute Imec presented the first power-performance area comparison between SRAM and STT-MRAM last-level cache at the 5 nm node.
The analysis, based on design-technology co-optimization and silicon verified models, reveals that STT-MRAM meets the performance requirements for last-level caches in the high-performance computing domain. For larger memory densities, STT-MRAM was found to offer significant energy gains compared to SRAM.
Posted: Dec 04,2018 by Ron Mertens