TSMC announced, during the company's virtual European technology symposium, that it is developing MRAM technologies for its 16nm FinFET platform. The company expects to offer flash-like configuration risk production starting in 4Q21 and RAM-like risk production scheduled for 4Q22.
In June 2017 it was reported that Taiwan Semiconductor Manufacturing Company (TSMC) will start producing embedded MRAM in 2018 using a 22 nm process. In what may bet he first adoption of TSMC's eMRAM technology, AI accelerator startup Gyrfalcon Technology announced the commercial availability of its LightSpeeur 2802M, AI ASIC that include TSMC's eMRAM.
The 2802M ASIC has 40MB of eMRAM memory, which can support large AI models or multiple AI models within a single chip. Applications include image classification, voice identification, voice commands, facial recognition, pattern recognition and more.
According to reports, Taiwan Semiconductor Manufacturing Company (TSMC) is aiming to start producing embedded MRAM chips in 2018 using a 22 nm process. This will be initial "risk production" to gauge market reception.
TSMC also aims to start embedded RRAM chip production in 2019.
A government-funded Taiwanese research institute says it will have phase-change memory products out within three years, while another memory technology to rival DRAM (dynamic RAM), magnetoresistive RAM (MRAM), may be available by the end of 2008.
TSMC and ITRI are working on MRAM technology. The two have been awarded over 40 patents related to MRAM technology, said Chang. TSMC will likely have the technology ready and available for customers by the end of next year or early in 2009, he said.
MRAM combines the ability to retain data when power is shut off with fast processing speeds comparable to DRAM. DRAM is speedy, but it cannot retain data without electrical power.
TSMC claims to have developed novel MRAM structures based on a 0.18-micron process and a pillar write word line (PWWL) cell. The company proposes to shrink the bit size by a "so-called ExtVia process" while reducing the writing current by a factor of two.
Toshiba and NEC jointly presented a paper on a low-power 6F2 MRAM based on a cross-point cell. The 1-megabit MRAM chip is said to have been manufactured in a 130-nm process and a 0.24 x 0.48-micron2 magnetic tunnel junction technology. The chip is said to have a 250-ns access time and 1.5-volt operations. "To suppress the sneak current, a cell design is proposed for the new (cross-point) cell with a hierarchical bit line architecture".
TSMC will handle the front-end of the MRAM manufacturing process, and the Electronics Research and Service Organization (ERSO) of ITRI will handle the back-end processes at its own lab, ITRI said.