One year ago, the French National Research Agency (ANR) launched an MRAM project called MARS (MRAM based Architecture For Reliable and low power Systems). The main focus of this project is the study of MRAM technology's contribution to embedded processors architectures. MARS also aims to build new MRAM architectures and design new software models.
The MARS project already reached several milestones:
- An open-source, generic STT and TAS compact Model (Spinlib library) for electrical simulation
- Developed new Non-Volatile Flip Flop (several patents were already requested) and a new non-volatile SRAM/MRAM memory (also patented)
- A full study on reliability on the STT-MRAM comprising noise and stochastic effects
- A study on the use of MRAM on the embedded processor hierarchy (MRAM cache memory based architecture)
- New MRAM/DRAM cells was designed and successfully tested on silicon
The 3-year project is mostly (€900,000 out of €1.5 million) funded by the ANR. The project is headed by the LIRMM (Laboratory of Informatics, Robotics, and Microelectronic of Montpellier, University of Montpellier) and its partners are EADS, SPINTEC lab, IEF and LRI lab (a cross faculty between University of Paris Sud and CNRS) and CEA-LIST.