This book provides an introduction to MRAM for microelectronics engineers written by specialists in magnetic materials and devices. The book presents the basic phenomena involved in MRAM, the materials and film stacks being used, the basic principles of the various types of MRAM (toggle and STT; magnetized in-plane or perpendicular-to-plane), the back-end magnetic technology, and recent developments toward logic-in-memory architectures.
Researchers at IMEC developed a 8nm perpendicular magnetic tunnel junction (pMTJ) with 100% tunnel magnetoresistance (TMR) and a magnetic coercive field up to 1,500 Oe in strength. The researchers also demonstrated integrated 1Mbit STT-MRAM 1T1MTJ arrays with pitches down to 100 nm.
IMEC says that this is the world's smallest pMTJ - which paves the way for high density stand-alone MRAM applications. The pMTJ was developed on 300mm silicon wafers in a production process that is compatible with the thermal budget of standard CMOS back-end-of-line technology.
This book presents an an energy-efficient in-memory computing platform based on a spintronics design. It details the models of spin-transfer torque magnetic tunnel junction and racetrack memory and shows how spintronics could be a candidate for future data-oriented computing for storage, logic, and interconnect.
The book then describes an implementation of in-memory AES, Simon cipher and interconnect. Finally it demonstrates in-memory-based machine learning and face recognition algorithms.
In 2015, the EU launched the GREAT project, with an aim to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting STT-MTJs to a single baseline technology in the same system on chip. GREAT stands for heteroGeneous integRated magnetic tEchnology using multifonctionnal stAndardized sTack.
The project partners now announced the first hybrid CMOS/MSS-MRAM Tape Out with Israel-based Tower Jazz. This hybrid integrated circuit uses the 180nm CMOS process from Tower and an academic MRAM post-process that will be done by CEA Spintec within their facilities.
Everspin announced its financial results for Q3 2016. Revenues reached $7.1 million (slightly up from $7 million in Q3 2016) and net loss was $1.4 million (down from $4.5 million in Q3 2015).
Everspin reports that its first generation toggle-MRAM product revenues grew 9% in the first three quarters of 2016 compared to 2015.
Capres A/S was established in 1999 in Denmark to develop a unique probe technology designed for in-line production monitoring in the semiconductor industry. The company, in collaboration with IBM, developed a resistivity measurement technique to characterize MTJ stacks.
Bo Svarrer Hansen, the company's CEO since 2002, was kind enough to answers a few questions we had, and share with us his views on the MRAM market and the company's measurement systems for MRAM and STT-MRAM device developers.
Q: Can you update us on Capres' current offers to the MRAM industry?
Capres customers are using our CIPTech® tools for R&D on small samples as well as volume production on 300 mm wafers. Depending on the configuration the tools measure with an in- plane or an out- of- plane magnetic field on blanket as well as patterned wafers.
STT-MRAM developer Avalanche Technology announced that volume production of its pMTJ STT-MRAM chips on 300 mm wafers will begin in early 2017. Avalanche started to sample 32Mb and 64Mb STT-MRAM chips in 2015
Avalanche has entered into a manufacturing agreement with Sony Semiconductor Manufacturing Corporation (SSMC) for this volume production. Avalanche targets several markets, including Storage, Automotive, IoT and embedded applications. Avalanche will offer discrete MRAM chips from 4Mb to 64Mb in size.