MRAM research or technical information

New USMR MRAM structure promises extremly simple design

Researchers from Tokyo's Institute of Technology (Tokyo Tech) developed a new MRAM cell structure (called USMR MRAM) that features a very simple structure with only two layers - which could hopefully enable lower-cost MRAM devices.

USMR MRAM cell structure image

The new design uses a combination of a topological insulator with a ferromagnetic semiconductor which enables a giant unidirectional spin Hall magnetoresistance (USMR).

New super-lattice SL-STT-MRAM enable faster and more efficient memory architecture

Researchers from the National Taiwan University developed a new ultra low power STT-MRAM architecture, called Super Lattice STT-MRAM, or SL-STT-MRAM. The researchers say that SL-STT-MARM simultaneously achieves ultra-high MR ratio, high-speed switching, and low RA.

SL STT MRAM structure

An SL-STT-MRAM is based on an SL-STT-MTJ, which uses a superlattice barrier to replace the single crystalline (MgO) barrier in traditional STT-MTJ. The superlattice barrier is made of alternating metal and insulator layers, in which only amorphous rather than single crystalline is used in the insulator. The SL-STT-MRAM features higher reliability for repeated writing than compared to traditional MgO based STT-MRAM.

Intel researchers demonstrate 2MB STT-MRAM arrays suitable for on-chip L4 cache applications

Intel researchers have demonstrated 2MB STT-MRAM devices that are suitable for on-chip L4 cache applications. Intel says these devices feature data retention, endurance and bit error rates good enough for L4 cache.

Intel slide - STT MRAM L4 Cache

Intel's new STT-MRAM features 20 nm write times, 4 ns read times, an endurance of 1012 cycles and memory retention of one second at 110 degrees. The bit rates are good enough to be handled with error-correcting code (ECC) techniques. To achieve these features, Intel reduced the magnetic junction size to 55 nm (from 70-80 nm it had achieved before).

Researchers in Japan developed a high-speed SOT-MRAM memory cell compatible with 300mm Si CMOS technology

Researchers at Tohoku University demonstrated a high-speed spin-orbit-torque MRAM (SOT-MRAM) memory cell compatible with 300 mm Si CMOS technology.

The SOT device achieved high-speed switching (down to 0.35 ns) and a high thermal stability factor (E/kBT 70) which the researchers say is sufficient for high speed non-volatile memory applications. The device can withstand annealing at 400°C. The researchers used these devices to create a complete SOT-MRAM memory cell.

Researchers demonstrate a new memory device using an OLED and a MOS capacitor

Researchers from TU Dresden developed a novel memory device that is based on a combination of an light emitting material and a metal-oxide semiconductor (MOS) capacitor.

pinMOS memory structure (TU Dresden)

The so-called pinMOS device is a non-volatile memory-capacitor with high repeatability and reproducibility. pinMOS devices can store several states, since charges can be added or removed in controllable amounts. This device can also be controlled (read and write) both electrically and optically. The light emitting material is an OLED device.

Optically-assisted MRAM could outperform current MRAM devices by a factor of 1000

Researchers from the Moscow Institute of Physics and Technology developed a new MRAM architecture that is based on THz pulses which are used to change the spin state. This so-called optically-assisted MRAM is extremely efficient (the power required to switch a "bit" will be a thousand times smaller compared to current MRAM devices) and fast.

The researchers use picosecond-long pulses (3 picoseconds = one light oscillation cycle) on a specially developed structure comprised from micrometer-sized gold antennas deposited on a thulium orthoferrite sample. The researcher admit that the material is excellent for fundamental research, but it may be too early to tell whether it could be used in the future for commercial applications. The researchers tell us that they re trying to raise funds now to start fundamental studies of this new optically-assisted MRAM.

Hprobe teams up with IMEC to develop SOT-MRAM testing tools

Hprobe, a developer of testing equipment for magnetic devices, announced that it has teamed up with the IMEC research institute to jointly extend Hprobe's fast testing protocols for SOT-MRAM devices.

Hprobe wafer prober system photo

Hprobe has already begun to optimize its test flow for SOT-MRAM devices in order to bring the characterization and testing to an industrial level with the primary objective to reduce the testing time while maximizing yield.

NTHU researchers manage to manipulate exchange bias by spin-orbit torque

Researchers from Taiwan's National Tsing Hua University (NTHU)managed to use a spin current to manipulate the exchange bias in Spin-Orbit Torque memory (SOT-MRAM). The researchers say that this has been a long-time challenge in the field.

MRAM chip Manipulating exchange bias by spin-orbit torque (NTHU)

To achieve this, the researchers added a platinum layer under the ferromagnetic and antiferromagnetic layers of the MRAM device. The researchers patented this technique before publishing their findings.

Tohoku University researchers develop the world's fastest STT-MRAM

Researchers from Japan's Tohoku University developed a 128 Mb STT-MRAM device that features a write speed of 14 nm, the world's fastest STT-MRAM chip at a density over 100 Mb.

Tohoku 128 MB STT-MRAM 14 ns write speed image

To achieve this high speed, the researchers developed MTJs that are integrated with CMOS, which also significantly reduces the power-consumption of the memory device.