A new European project aims to develop a system-level STT-MRAM exploration flow

The EU launched a new project called GREAT H2020 moderated by the CEA-Spintec laboratory that plans to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS thanks to a single baseline technology in the same System on Chip.

MAGPIE process image

One of the project’s final objectives is to develop a system-level simulation and design of a representative IoT platform, integrating this technology. To achieve it, a unique exploration flow is proposed: MAGPIE. MAGPIE stands for Manycore Architecture enerGy and Performance evaluation Environment and has been jointly developed and funded through GREAT and the CONTINUUM ANR French project.

It is built upon three mature and popular tools: the gem5 full-system simulator, the McPAT and NVSim power/energy and area estimation tools for CMOS, SOI and NVM technologies. MAGPIE, developed by LIRMM (joint research united of the University of Montpellier and CNRS), is a holistic academic design evaluation tool which aims at integrating emerging NVM technologies in manycore systems.

MAGPIE explorer enables a designer to specify input design specifications and run a seamless evaluation flow that automatically produces results including application outputs, performance numbers, area, power and energy consumption.

Posted: Oct 12,2017 by Ron Mertens