Researchers from the A*STAR Institute of Materials Research and Engineering and the National University of Singapore have developed an improved design for a Graphene based field-effect transistor (FET). The new device includes an additional silicon dioxide (SiO2) dielectric gate below the graphene layer. This allows for simplified bit writing by providing an additional background source of charge carriers and paves the way towards nonvolatile Graphene-based memory.

Improved graphene–ferroelectric FET with SiO2 basal layer illustration

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