Event Duration:
Where:
Event duration
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Where
Takeda Hall, the University of Tokyo, Tokyo, Japan
The conference will presnet original papers about new developments in silicon, III-V compounds, and nanotechnology microelectronics test structure research, implementation, and applications as well as test structures aimed at new materials and devices characterization are solicited.
One of the topics - evaluation of MRAM, RRAM, FeRAM, SRAM, NVM, and SOI-Based Memory cells, evaluation and optimization of standard cell macros and other product circuits. Low Noise Amplifier and other RF product testing.