Everspin announced a new MRAM chip, the 1-Megabit serial MR10Q010 that features a Quad-SPI interface. Quad SPI, which has four serial I/O paths, is an evolutionary upgrade from SPI (that has a single I/O path). Everspin expects the new part, which has a 104 MHz clock speed with 52 MBps read/write bandwidth, to be used in applications that require high frequency, high-performance writes of most critical data.
The MR10Q010 MRAM offers read/write bandwidth comparable to parallel I/O MRAM but with a significant savings in pins and allows execute in place (XIP) operation. The chip includes a complete command set for Quad SPI operations including fast reads and writes in which address and data are input on all four I/Os to reduce clock cycles. The part comes in a cost-effective, low pin count 16-pin SOIC package â a savings of 20 pins over parallel interfaces â that supports low voltage levels with separate VDDQ for I/O. It is compatible with future high-density Quad SPI packages that Everspin is planning to introduce.