June 2014

Researchers from New Zealand's Victoria University are developing MRAM devices (MTJs) based on rare earth nitrides (RENs). RENs, grown under ulta-high vacuum are both magnetic and semiconducting.

The team is basing its work on europium nitride, which is not usually magnetic, but has been "tricked" into behaving like a magnet by being produced with slightly too few nitrogen atoms. Those RENs are grown in France's Centre for Research on Hetero-Epitaxy and Applications.

One of the problems with flash memory is that it is sensitive to defects. To solve this problem, researchers from Samsung Electronics are developing flash devices based on graphene quantum dots (GQDs). The performance of such a device is promising, with an electron density that is comparable to semiconductor and metal nanocrystal based memories. Those flash memory can also be made flexible and transparent.

The researchers used GQDs in three different sizes (6, 12, and 27 nm) between silicon dioxide layers. The memory of the QDs depend on their sizes: the 12 nm dot for example offers the highest program speed while the 27 nm dot has the highest erase speed, and is also the most stable. Samsung says that this is the first GQD demonstration in a practical device.

Nantero has been developing NRAM (carbon nanotube based memory) for a long time, and now they collaborated with researchers from Chuo University to show how this memory features high-speed, low-power-consumption and high-reliability operation.

An NRAM memory cell is made from a thin CNT film sandwiched between two metal electrodes. When voltage is applied, the CNTs come closer to each other (due to electrostatic force and intermolecular force) and the resistivity is lowered. When the voltage drops to zero, the CNTs do not separate as they are tightly attached. This creates a non-volatile memory. To seperate the CNTs, a phonon is generatd using a high voltage.

Toshiba developed new STT-MRAM technology that can be used to enable MRAM based cache memory for microprocessors. The L2 cache alone uses about 80% of the power consumed by the CPU, so reducing the power consumption of the cache is very important - and STT-MRAM may reduce this consumption by about 60%. It's not clear how close is this technology to actually being commercialized.

Toshiba's new STT-MRAM uses a dual-cell (2T-2MTJ) circuit in which the two MTJs have complementary resistive states (high and low resistive states). This eliminates the leak path and also increases the readout signal intensity - and so improves access speed. In Toshiba's cahce, the read time is 4.1 ns - very close to that of SRAM, while the write time (2.1ns) is similar to SRAM. Toshiba also implemented error correction mechanisms into the cache STT-MRAM chip.