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MRAM research or technical information

Researcher develop a simpler, faster and more efficient MRAM using half-way magnetic flipping

Chinese researchers have shown that magnetic memory (MRAM), logic and sensor cells can be made faster and more energy efficient by using an electric, not magnetic, field to flip the magnetization of the sensing layer only about halfway, rather than completely to the opposite direction.

The new cell requires only two layers (traditional MRAM requires three or more layers) - and so hopefully will be easier and cheaper to make. The design is a simple thin-layer sandwich of two different materials, each of which has very different magnetic and electrical properties. Applying a voltage to the ferroelectric layer switches its polarization in a way that starts to change the magnetic orientation of the adjacent ferromagnetic layer. This partial change alters the electrical resistance of the entire stack enough to indicate whether the cell is storing a "0" or a "1" data bit.

via PhysOrg

Magsil finally out of stealh-mode, plans to make 1Mb MRAM chips soon

MagSil LogoMagSil has been working on MRAM since 2004, but we had very little information about the company till now (except for a PR from 2009 in  which they said they'll soon reach full-scale commercialization). Today they have finally revealed more information. They are developing MRAM based on Magnetic Recording (iMR) cell architecture, based on a traditional magnetic tunnel junction (MTJ) scheme.

The company hopes to start making a standalone 1Mb MRAM device (based on 130- and 90-nm processes)  "pretty soon". They also have plans for a 64Mb chip.

The technology was originally developed by MIT and exclusively licensed to Magsil. They have filed several suits against companies over hard disk drive components using tunneling magnetoresistive (TMR) technology  and have reached settlements with Western Digital, Seagate, SAW Magnetics and Headway Technologies. Litigation is still ongoing with Hitachi and Shenzen ExcelStor technology.

Scientists created a plastic memory device that uses electron spin to read/write data

Scientists from Ohio University has created a new spintronics memory device from plastic. It’s simply a thin strip of dark blue organic-based magnet layered with a metallic ferromagnet and connected to two electrical leads. Still, the researchers successfully recorded data on it and retrieved the data by controlling the spins of the electrons with a magnetic field. They say that the new device is a bridge between today’s computers and the all-polymer, spintronic computers that the researchers hope to eventually create.

PNNL Plastic spintronics memory image

Via Spintronics-Info

Researchers create a new STT-RAM composite structure, reduces current by a factor of 50

Researchers from the University of Minnesota are proposing a new composite structure for STT-RAM devices that reduces current densities by up to a factor of 50. According to the researchers, the major issue with STT-RAM is the high power inputs it requires, and the degradation of the storage elements due to the heat created from these high power inputs. The researchers hope that the new structure will pave the way for STT-RAM to become a universal memory.

The composite structure is formed by inserting one or more soft assisting layers between the recording layer and the layer with a permanent polarity. The soft assisting layers have smaller polarities than the recording layer with each assisting layer closer to the recording layer having a stronger polarity than the previous layer.

Spin Transfer Technologies and Singulus to collaborate on STT-RAM

Spin Transfer Technologies (STT) and Singulus Technologies will collaborate to apply advanced deposition techniques to support commercial development of STT’s novel MRAM memory devices. The companies will use Singulus TIMARIS deposition tool to create magnetic layer stacks with STT’s design specifications. These layer stacks will then be processed at STT contracted facilities into memory arrays for testing, optimization, and eventually, pre-commercial prototyping.

Singulus has already sold several TIMARIS systems for MRAM companies (including Grandis and Crocus). STT is working towards Orthogonal Spin Transfer MRAM or OST-MRAM for short. Back in October 2008 we have interviewed Vincent Chun, the executive in charge at Spin Transfer Technologies.

Aeroflex licenses MRAM technology from Everspin, to make memory solutions for aerospace and defense applications

EverSpin logoAeroflex Colorado Springs has licensed MRAM technology from Everspin for the development of HiRel nonvolatile memory solutions for aerospace and defense applications. Aeroflex will develop 4Mb and 16Mb MRAM monolithic solutions with guaranteed total ionizing dose and single event effect hardness. Aeroflex envisions HiRel MRAM solutions being used with microprocessors, DSP engines, storage systems, instruments, and reconfigurable FPGAs that require guaranteed total ionizing dose and single event hardness.

Aeroflex’s MRAM roadmap includes a family of -55oC to +125oC, QML products offered in ceramic packages per a Standard Microcircuit Drawing (SMD). As a replacement for 3.3 volt asynchronous SRAM, Aeroflex products will be 8-bit parallel I/O solutions in densities of 4M, 16M, and 64Mbit. All products are designed to operate from a single 3.3 volt supply. With data retention after each write of 20 years and infinite read/write endurance, Aeroflex MRAM products are ideal for working memory applications that require high rates of data overwrites.

Hitachi and Tohoku university developed MLC STT-MRAM

Hitachi and Tohoku University have developed n STT-RAM that can be written using multi-level cell (MLC) technology. They actually call their technology SPRAM (spin-transfer torque memory).

The idea is to three-dimensionally stack two TMR elements and connect them in series. This creates , four-value memory (2 bits per cell). Hitachi has already produced a prototype of this memory. The biggest advantage of the MLC SPRAM is that it can reduce bit costs in proportion to the number of stacked TMR elements, Hitachi said. For example, when two TMR elements are stacked, bit costs are reduced by about half.


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