STT-RAMResearchers create a new STT-RAM composite structure, reduces current by a factor of 50Researchers from the University of Minnesota are proposing a new composite structure for STT-RAM devices that reduces current densities by up to a factor of 50. According to the researchers, the major issue with STT-RAM is the high power inputs it requires, and the degradation of the storage elements due to the heat created from these high power inputs. The researchers hope that the new structure will pave the way for STT-RAM to become a universal memory. The composite structure is formed by inserting one or more soft assisting layers between the recording layer and the layer with a permanent polarity. The soft assisting layers have smaller polarities than the recording layer with each assisting layer closer to the recording layer having a stronger polarity than the previous layer.
Spin Transfer Technologies and Singulus to collaborate on STT-RAMSpin Transfer Technologies (STT) and Singulus Technologies will collaborate to apply advanced deposition techniques to support commercial development of STT’s novel MRAM memory devices. The companies will use Singulus TIMARIS deposition tool to create magnetic layer stacks with STT’s design specifications. These layer stacks will then be processed at STT contracted facilities into memory arrays for testing, optimization, and eventually, pre-commercial prototyping. Singulus has already sold several TIMARIS systems for MRAM companies (including Grandis and Crocus). STT is working towards Orthogonal Spin Transfer MRAM or OST-MRAM for short. Back in October 2008 we have interviewed Vincent Chun, the executive in charge at Spin Transfer Technologies.
Hitachi's VP of engineering moves to Grandis
Grandis has been recently awarded a $8.6 million project for STT-RAM chip development from US's DARPA.
Everspin names Phillip LoPresti as president and CEO
“I am looking forward to building on MRAM’s success across multiple markets and leading Everspin through the next stage of our technology development,” said Phillip LoPresti. “Our strong product portfolio and proven track record positions us to expand market share as more customers recognize the value of our products. Everspin is focused on leveraging its MRAM expertise and resources to accelerate the introduction of new products in development based on our next-generation, high density Spin Torque MRAM technology.”
Hitachi and Tohoku university developed MLC STT-MRAMHitachi and Tohoku University have developed n STT-RAM that can be written using multi-level cell (MLC) technology. They actually call their technology SPRAM (spin-transfer torque memory). The idea is to three-dimensionally stack two TMR elements and connect them in series. This creates , four-value memory (2 bits per cell). Hitachi has already produced a prototype of this memory. The biggest advantage of the MLC SPRAM is that it can reduce bit costs in proportion to the number of stacked TMR elements, Hitachi said. For example, when two TMR elements are stacked, bit costs are reduced by about half.
Grandis awarded $8.6 million from DARPA for a 2nd phase STT-RAM research project
Phase 2 will focus on test of verification of STT-RAM integrated memory arrays.
Fujitsu developed a new STT-MRAM cell that is 60% smaller and is easier to integrateFujitsu Laboratories has developed a new memory cell circuit for STT-MRAM that reverses the typical order of magnetic tunnel junctions (MTJ) to enable a space savings of 60% and achieve a greater degree of integration The memory cell circuit in spin-torque-transfer MRAM is a circuit that connects the MTJ element with a cell-select transistor, which act as switches that select which MTJ elements to write to or read from. With existing memory cell circuits, when the MTJ element of a spin-torque-transfer MRAM has been written to a high-resistance state ("1"), voltage is lowered through variable resistance - this requires a larger current to write than when an MTJ element it is switched to a low resistance state ("0"), which is not affected by variable resistance. In other words, because the cell-select transistor's current-driving capability is low, writing to a high-resistance state ("1") would require a significant current. As such, even with a low driving-current capability, cell-select transistors need to be relatively large to ensure an adequate write current, which has been a barrier to reducing transistor size.
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