STT-RAM

Fujitsu Laboratories and the University of Toronto announced that they have jointly developed the world's first high-reliability read-method for use with spin-torque-transfer (STT) MRAM that is insusceptible to erroneous writes.

STT-MRAM circuit embedded in a CMOS chip

The newly developed read-method uses a negative resistance that is intermediate between the MTJ's high resistance and low resistance on a parallel circuit. If the MTJ is in a high-resistance state, this circuit exhibits negative-resistance characteristics. If the MTJ is in a low-resistance state, then it exhibits normal-resistance characteristics. These characteristics allow the resistance value to be read at lower voltages than before, suppressing the tendency of the read operation to reverse the direction of magnetization and avoiding the problem of erroneous write operations.

Fujitsu Laboratories and the University of Toronto plan to continue with R&D related to STT MRAM to strive toward practical implementation, such as lowering write currents and developing process technologies for further miniaturization.

Researchers from Japan's AIST institute have developed a new Tunnel-Magnetoresistance (or TMR) element with a low data writing current and high data stability. This kind of TMR is required for high-capacity MRAM. In fact the team says that this TMR can be used to make perpendicular STT-MRAM with densities of over 10GBit. 

With existing TMRs, there's a trade-off between data writing current and data stability. Data loss happens if the free-layer's magnetization is reversed because of thermal agitation, and if you make a thicker free-layer it solves the data-loss issues, but you need more current. The new design solved this issue by using a free layer that is made from a nonmagnetic layer between two ferromagnetic layers. The resistance to thermal agitation is improved - it is five times better, while the current is only increased by 80%. 

The team used an in-plane magnetization film for the free layer, which can be used to make a 1-Gbit MRAM. They plan to make the current even lower with a perpendicular magnetization film, which will allow for a 10 Gbit MRAM device.

Via TechOn

The Korean Government has decided to fund STT-RAM research for Hynix and Samsung in a $40 million project. The government will pay around half of the sum for the project, which is intended to run till 2014. The project calls for the government to work with Samsung and Hynix together for research and development on STT-MRAM chips. Korea aims to control around 45% of the 30-nano type memory chip market by 2015.

The companies have already opened a new laboratory at Hangyang University's fusion technology center. It is already equipped with a fully operational 300mm magnetic thin film deposition system and other chip-making facilities.

Via YonHap news

Crocus Technology announced the development of a new STT-MRAM technology with a minimum feature size of 50nm that will deliver on the promise of using STT memory in high-density memory applications, that will be competitive with DRAM and NOR-Flash.

Researchers from NY University, together with Spin Transfer Technologies have demonstrated magnetic vector switching for current pulses as short as 100 picoseconds. This is among the shortest write times reported by developers of MRAM devices.

The final day of the Flash Memory Summit started with a panel on new memory technologies.

Crocus Technologies presented their TAS MRAM design which is targeted at SRAM and flash applications. Their product compared to SRAM at a 25% smaller cell, adding Non-Volatile capability, and a zero standby current.  The product compared to NAND flash by having a smaller cell and only 1X area overhead for controlling circuitry. It is currently being built on a 130nm node and can be scaled. It is targeted at Cache memory, data logging, medical instrumentation, casino gaming and industrial control applications.  They are targeting several business models - selling the standard product ICs, licensing IP a process technology licensing service and providing a foundry service.

Avalanche Technology and Integral Solutions International (ISI) have designed a Wafer Level Analyzer, the WLA-3000, to be used in STT-MRAM development. 

The WLA-3000 includes specific hardware test modules including nS-range Pulse Generator that quickly measures switching currentse of MTJ devices in STT-MRAM as a function of Pulse Width. Using this Pulse Generator module, customers will be able to perform Error Rate, Switching Probability, Endurance Testing, and Read/Write Disturb analysis in a fraction of time as compared to other slower pulsers.

A couple of days ago we reported that NEC are working towards perpendicular MRAM using 2T1MTJ... now we have some more info, thanks to TechOn.

NEC and NEC Electronics employed a new method called "spin torque domain wall displacement write method" to reduce write current and realize microfabrication at the same time. In fact, they aim to reduce the current by as much as 90%. They were also able to increase speed to 500Mhz. This technology is not 'new', it was announced in 2007, but now they have a test chip ready.

A japanese site reports that NEC are working towards a perpendicular MRAM cell using "2T1MTJ" technique. NEC are apparently using a 55nm process.

Details are not very clear as the translation is not so good... Hopefully more details will emerge soon.

Crocus announced today that it has implemented CIPtech, the newest tool from CAPRES A/S, for enabling measurements associated with advanced Spin Torque Technology (STT). This unique new tool, designed especially for the MRAM and magnetic recording Read Head industries, enables Crocus to determine tunneling resistance on MTJ films prior to final test. With this upgrade, measurement that used to require weeks of sample preparation can now be performed within minutes.