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Toshiba - advances in 1Gb MRAM. Expects MRAM to take over DRAM in 2015

Toshiba is still working on 1Gb MRAM chips, and it's "almost ready". They are using Spin-RAM (STT-RAM), like IBM.

Toshiba's projections sees MRAM taking over DRAM in 2015.

Read more here (TechRadar) 

Toshiba develops new MRAM device which opens the way to giga-bits capacity

Toshiba Corporation today announced important breakthroughs in key technologies for MRAM. The company has successfully fabricated a MRAM memory cell integrating the new technologies and verified its stable performance.

In making these major advances, Toshiba applied and proved the spin transfer switching and perpendicular magnetic anisotropy (PMA) technologies in a magnetic tunnel junction, which is a key component in the memory cell.

Toshiba and NEC Develop World's Fastest, Highest Density MRAM

Toshiba Corporation and NEC Corporation today announced that they have developed a magnetoresistive random access memory (MRAM) that combines the highest density with the fastest read and write speed yet achieved. The new MRAM achieves a 16-megabit density and a read and write speed of 200-megabytes a second, and also secures low voltage operation of 1.8V.

MRAMs shift paths at VLSI forum

Long considered a potential next-generation memory, magnetoresistive RAM was in the spotlight at last week's VLSI symposium.
Fujitsu Laboratories Ltd. and the team of NEC Corp. and Toshiba Corp. presented new approaches to MRAM circuitry and cell structure, respectively. The companies said they were establishing essential technologies for MRAMs, which are nonvolatile, blessed with unlimited read/write cycles and expected to enter practical widespread use around 2008.
NEC and Toshiba formed a joint R&D MRAM project in 2002. At last week's symposium, the team proposed a toggle-mode MRAM cell. Its magnetic tunnel junction with a multilayered structure, the team said, solves the toggle-switching issue.

TSMC, NEC, Toshiba describe novel MRAM cells

TSMC claims to have developed novel MRAM structures based on a 0.18-micron process and a pillar write word line (PWWL) cell. The company proposes to shrink the bit size by a "so-called ExtVia process" while reducing the writing current by a factor of two.
Toshiba and NEC jointly presented a paper on a low-power 6F2 MRAM based on a cross-point cell. The 1-megabit MRAM chip is said to have been manufactured in a 130-nm process and a 0.24 x 0.48-micron2 magnetic tunnel junction technology. The chip is said to have a 250-ns access time and 1.5-volt operations. "To suppress the sneak current, a cell design is proposed for the new (cross-point) cell with a hierarchical bit line architecture".


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