NEC

There's an interesting article at Tech-On, by NEC, on their MRAM-based magnetic flip flip (MFF). NEC say that using such flip-flops can make low power  'standby' mode for appliances (TVs, computers, portable devices...).

Today, for example, LCD TVs have two kinds of standby - "fast standby" which consumes as much as 15W, and 'slow standby' that may consume as low as 0.1W, but may take a few seconds to show a picture when powered back on. The MFF might make it possible to design a stand-by mode that is both fast to power on, and uses minimal power.

A couple of days ago we reported that NEC are working towards perpendicular MRAM using 2T1MTJ... now we have some more info, thanks to TechOn.

NEC and NEC Electronics employed a new method called "spin torque domain wall displacement write method" to reduce write current and realize microfabrication at the same time. In fact, they aim to reduce the current by as much as 90%. They were also able to increase speed to 500Mhz. This technology is not 'new', it was announced in 2007, but now they have a test chip ready.

A japanese site reports that NEC are working towards a perpendicular MRAM cell using "2T1MTJ" technique. NEC are apparently using a 55nm process.

Details are not very clear as the translation is not so good... Hopefully more details will emerge soon.

NEC has announced it managed to make a 1-bit Magnetic Flip Flop (MFF, as they like to call it). Unlike existing flip-flops, it does not need power to retain the value.

NEC suggests using such flip-flops instead of regular ones, and using MRAM instead of SRAM and you can make a system on a chip that does not need power to store data. MRAM is better than FLASH, says NEC, because of the unlimited write cycles.

NEC's MFF opereates at 1.2V or less, like regular flip-flops. The clock speed can be up to 3.5GHz.

Via Register Hardware

Toshiba Corporation and NEC Corporation today announced that they have developed a magnetoresistive random access memory (MRAM) that combines the highest density with the fastest read and write speed yet achieved. The new MRAM achieves a 16-megabit density and a read and write speed of 200-megabytes a second, and also secures low voltage operation of 1.8V.

In an effort to someday profit off of the manufacturer of surface-conduction electron-emitter display or SED devices, Canon yesterday bought 53.9% of NEC Machinery and all of NEC Machinery’s shares in Anelva Corp., a subsidiary of NEC Corp. Anelva is a japanese company that manufactures major equipment for the fabrication of semiconductors and LCDs using vacuum technology. Anelva developed a 200- to 300-mm-wafer-compliant deposition (sputtering) equipment for MRAM, the C-7100, using their unique low-pressure plasma deposition technique.

Read more here

Long considered a potential next-generation memory, magnetoresistive RAM was in the spotlight at last week's VLSI symposium.
Fujitsu Laboratories Ltd. and the team of NEC Corp. and Toshiba Corp. presented new approaches to MRAM circuitry and cell structure, respectively. The companies said they were establishing essential technologies for MRAMs, which are nonvolatile, blessed with unlimited read/write cycles and expected to enter practical widespread use around 2008.
NEC and Toshiba formed a joint R&D MRAM project in 2002. At last week's symposium, the team proposed a toggle-mode MRAM cell. Its magnetic tunnel junction with a multilayered structure, the team said, solves the toggle-switching issue.

TSMC claims to have developed novel MRAM structures based on a 0.18-micron process and a pillar write word line (PWWL) cell. The company proposes to shrink the bit size by a "so-called ExtVia process" while reducing the writing current by a factor of two.
Toshiba and NEC jointly presented a paper on a low-power 6F2 MRAM based on a cross-point cell. The 1-megabit MRAM chip is said to have been manufactured in a 130-nm process and a 0.24 x 0.48-micron2 magnetic tunnel junction technology. The chip is said to have a 250-ns access time and 1.5-volt operations. "To suppress the sneak current, a cell design is proposed for the new (cross-point) cell with a hierarchical bit line architecture".