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Spin Transfer Technologies starts sampling 80nm OST-MRAM chips

Jan 26, 2017

Spin Transfer TechnologiesSpin Transfer Technologies announced that it started to deliver fully functional ST-MRAM samples to customers in North America and Asia.

The sample devices are based on the company's Orthogonal Spin Transfer Magneto-Resistive Random Access Memory technology (OST-MRAM), and use 80nm perpendicular magnetic tunnel junctions (MTJs)., the latest generation of MRAM technology.

The best of 2016 - top MRAM stories

Dec 27, 2016

2016 is soon over - and this was a very exciting year for the MRAM industry. Everspin floated on the Nasdaq and started sampling 256Mb STT-MRAM chips, other companies also announced and launched MRAM devices, and IBM announced that the "time for STT-MRAM is now". Interest in MRAM technologies is certainly on the rise!

Here are the top 10 stories posted on MRAM-Info in 2016, ranked by popularity (i.e. how many people read the story):

Toshiba and Hynix prototype a 4 Gb STT-MRAM

Dec 20, 2016

Toshiba and SK Hynix co-developed a 4-Gbit STT-MRAM chip, and presented a prototype at IEDM 2016.

Toshiba Hynix 4Gb STT-MRAM mTJ array photo

The prototype chip is made from eight 512-Mbit banks, and the cell area is equivalent to that of DRAM - at 9F2, which Hynix says is much smaller than conventional STT-MRAMs (50F2).

Samsung demonstrates a 8Mb embedded pMTJ STT-MRAM device

Dec 12, 2016

Samsung demonstrated an LCD display that uses a tCON chip that uses embedded 28nm pMTJ STT-MRAM memory, instead of the normally used SRAM. The MRAM device had a density of 8Mb and a 1T-1MTJ cell architecture. The cell size is 0.0364 um2.

Samsung LCD tCON Demo (IEDM-2017)

A tCON chip is a timing controller chip that processes the video signal input and processes it to generate control signal to the source & gate driver of the LCD display. The memory is used a a frame memory which stores previous frame data. Samsung prepared a test chip that contains both SRAM and MRAM memory devices to show that there is no difference between the two. SRAM replacement is a popular MRAM application.

IMEC researchers demonstrate the world's smallest pMTJ at 8nm

Dec 07, 2016

Researchers at IMEC developed a 8nm perpendicular magnetic tunnel junction (pMTJ) with 100% tunnel magnetoresistance (TMR) and a magnetic coercive field up to 1,500 Oe in strength. The researchers also demonstrated integrated 1Mbit STT-MRAM 1T1MTJ arrays with pitches down to 100 nm.

IMEC says that this is the world's smallest pMTJ - which paves the way for high density stand-alone MRAM applications. The pMTJ was developed on 300mm silicon wafers in a production process that is compatible with the thermal budget of standard CMOS back-end-of-line technology.

The EU-funded GREAT project presents its first hybrid CMOS-MRAM 180nm tape out

Nov 20, 2016

GREAT Project logoIn 2015, the EU launched the GREAT project, with an aim to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting STT-MTJs to a single baseline technology in the same system on chip. GREAT stands for heteroGeneous integRated magnetic tEchnology using multifonctionnal stAndardized sTack.

The project partners now announced the first hybrid CMOS/MSS-MRAM Tape Out with Israel-based Tower Jazz. This hybrid integrated circuit uses the 180nm CMOS process from Tower and an academic MRAM post-process that will be done by CEA Spintec within their facilities.

Everspin reports its financial results for Q3 2016

Nov 16, 2016

Everspin announced its financial results for Q3 2016. Revenues reached $7.1 million (slightly up from $7 million in Q3 2016) and net loss was $1.4 million (down from $4.5 million in Q3 2015).

Everspin reports that its first generation toggle-MRAM product revenues grew 9% in the first three quarters of 2016 compared to 2015.

Interview with Bo Hansen, CEO at Capres A/S

Oct 26, 2016

Bo Hansen, Capres CEOCapres A/S was established in 1999 in Denmark to develop a unique probe technology designed for in-line production monitoring in the semiconductor industry. The company, in collaboration with IBM, developed a resistivity measurement technique to characterize MTJ stacks.

Bo Svarrer Hansen, the company's CEO since 2002, was kind enough to answers a few questions we had, and share with us his views on the MRAM market and the company's measurement systems for MRAM and STT-MRAM device developers.

Q: Can you update us on Capres' current offers to the MRAM industry?

Capres customers are using our CIPTech® tools for R&D on small samples as well as volume production on 300 mm wafers. Depending on the configuration the tools measure with an in- plane or an out- of- plane magnetic field on blanket as well as patterned wafers.

Avalanche to commence volume pMTJ STT-MRAM production in early 2017

Oct 21, 2016

STT-MRAM developer Avalanche Technology logo Avalanche Technology announced that volume production of its pMTJ STT-MRAM chips on 300 mm wafers will begin in early 2017. Avalanche started to sample 32Mb and 64Mb STT-MRAM chips in 2015

Avalanche has entered into a manufacturing agreement with Sony Semiconductor Manufacturing Corporation (SSMC) for this volume production. Avalanche targets several markets, including Storage, Automotive, IoT and embedded applications. Avalanche will offer discrete MRAM chips from 4Mb to 64Mb in size.